ADMC401BST datasheet(16/60 Pages) AD

16 / 60 page

REV. B

ADMC401

–16–

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches from data memory and pro-

gram memory. Each DAG maintains and updates four address

pointers (I registers). Whenever the pointer is used to access

data (indirect addressing), it is post-modified by the value in

one of four modify (M) registers. A length value may be associ-

ated with each pointer (L registers) to implement automatic

modulo addressing for circular buffers. The circular buffering

feature is also used by the serial ports for automatic data trans-

fers to and from on-chip memory. DAG1 generates only data

memory addresses but provides an optional bit-reversal capabil-

ity. DAG2 may generate either program or data memory ad-

dresses, but has no bit-reversal capability.

Efficient data transfer is achieved with the use of five internal

buses:

• Program Memory Address (PMA) Bus.

• Program Memory Data (PMD) Bus.

• Data Memory Address (DMA) Bus.

• Data Memory Data (DMD) Bus.

• Result (R) Bus.

Program memory can store both instructions and data, permit-

ting the ADMC401 to fetch two operands in a single cycle, one

from internal program memory and one from internal data

memory. The ADMC401 can fetch an operand from on-chip

program memory and the next instruction in the same cycle.

The ADMC401 writes data from its 16-bit registers to the 24-

bit program memory using the PX register to provide the lower

eight bits. When it reads data (not instructions) from 24-bit

program memory to a 16-bit data register, the lower eight bits

are placed in the PX register.

The ADMC401 can respond to a number of distinct DSP core

and peripheral interrupts. The DSP core interrupts include

serial port receive and transmit interrupts, timer interrupts,

software interrupts and external interrupts. In addition, there is

a master

RESET signal. The motor control peripherals also

produce interrupts to the DSP core.

The two serial ports (SPORTs) provide a complete synchronous

serial interface with optional companding in hardware and a

wide variety of framed and unframed data transmit and receive

modes of operation. Each SPORT can generate an internal

programmable serial clock or accept an external serial clock.

Boot loading of both the program and data memory RAM of the

ADMC401 can be through the serial port SPORT1. Alterna-

tively the ADMC401 can be boot loaded from an external byte-

wide memory connected to the external address and data buses.

After reset, seven wait states are automatically generated. This

permits, for example, a 38.5 ns ADMC401 to use an external

250 ns EPROM as boot memory. The internal boot address

generator provides the addresses for booting from an external

byte-wide memory.

A programmable interval counter is also included in the DSP

core and can be used to generate periodic interrupts. A 16-bit

count register (TCOUNT) is decremented every n processor

cycles, where n-1 is a scaling value stored in the 8-bit TSCALE

rupt is generated and the count register is reloaded from a 16-

bit period register (TPERIOD).

The ADMC401 instruction set provides flexible data moves and

multifunction (one or two data moves with a computation)

instructions. Each instruction is executed in a single 38.5 ns

processor cycle (for a 13 MHz crystal). The ADMC401 assem-

bly language uses an algebraic syntax for ease of coding and

readability. A comprehensive set of development tools supports

program development.

Serial Ports

The ADMC401 incorporates two complete synchronous serial

ports (SPORT0 and SPORT1) for serial communications and

multiprocessor communication. The following is a brief list of

the capabilities of the ADMC401 SPORTs. Refer to the ADSP-

2100 Family User’s Manual, Third Edition for further details.

•

SPORTs are bidirectional and have a separate, double-

buffered transmit and receive section.

•

SPORTs can use an external serial clock or generate their

own serial clock internally.

•

SPORTs have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame synchronization signals are active high or inverted,

with either of two pulsewidths and timings.

SPORTs support serial data word lengths from 3 bits to 16

bits and provide optional A-law and

µ-law companding.

•

SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

•

SPORTs can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word. An inter-

rupt is generated after a data buffer transfer.

•

SPORT0 has a multichannel interface to selectively receive

and transmit a 24-word or 32-word, time-division multi-

plexed, serial bitstream.

•

SPORT1 can be configured to have two external interrupts

(

IRQ0 and IRQ1), and the Flag In and Flag Out signals. The

internally generated serial clock may still be used in this

configuration.

The following are additional capabilities of the ADMC401

SPORTs that are not part of the ADSP-21xx products:

•

SPORT1 is the input for single pin program and data

memory boot loading. The RFS1 pin can be configured

internally to the ADMC401 as an SROM/E

2PROM reset

signal.

•

SPORT1 has two data receive pins (DR1A and DR1B). The

DR1A pin is intended only for synchronous data receive

from the external E

2PROM. The DR1B pin can be used as

the data receive pin for a general purpose SPORT after boot-

ing or as the data receive pin for other boot load modes or as

the UART/debugger interface. The DR1A and DR1B pins

are internally multiplexed onto the one data receive pin of

the SPORT. The particular data receive pin selected is deter-

mined by Bit 4 of the MODECTRL register.

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