ADMC401BST datasheet(36/60 Pages) AD

36 / 60 page

REV. B

ADMC401

–36–

rate of 1.08 MHz. In general, the maximum encoder rate that

can be consistently recognized is given by:

ENCMAX

CLKOUT

×+

()

Operation of both the input synchronization logic and the

noise filters is shown in Figure 30 for the default case where

EIUFILTER(5::0) = 0x00 and the noise filters are clocked at

CLKOUT.

CLKOUT

EIA

EIB

EIAS

EIBS

3tCK

NOISE PULSE

1tCK

Figure 30. Operation of input synchronization and noise

filters of encoder interface with EIUFILTER(5:0) = 0x00

such that the filters are operated at CLKOUT.

The default value for EIUFILTER(5::0) following a power on

or reset is 0x00 so that the EIU filters are clocked at the CLK-

OUT rate and minimal filtering is applied. There is a direct

trade-off between the amount of filtering applied to the encoder

inputs and the maximum possible encoder signal rate. In effect,

the larger the value of EIUFILTER(5::0), the more filtering that

is applied to the encoder signals, so that, for a given number of

encoder lines, the maximum speed of rotation is lower.

The influence of the encoder filter on the zero marker signals

(EIZ and EIS) can be somewhat different that on the EIA or

EIB signals, depending on the exact nature of the encoder. In

common incremental encoders, the width of the zero marker

can be equal to a quarter, a half or a full period of one of the

quadrature signals (say EIA). Applying the three-stage delay

filter to a zero marker whose width is either equal to half or a

full quadrature pulse period does not change the achievable

maximum encoder rate. However, the maximum possible en-

coder rate is changed if the three-stage filter is applied in the

case where the width of the zero marker is equal to a quarter of

the EIA or EIB period. In this case the influence of the three-

stage delay filter is to effectively half the maximum encoder

signal rate to that described above (or 2.15 MHz for a 26 MHz

CLKOUT rate).

Encoder Counter Direction

The direction of quadrature counting is determined by Bit 0

(REV) of the EIUCTRL register. If the REV bit is cleared, the

signal at the EIA pin is fed to the A input to the quadrature

counter and the EIB pin is fed to the B input. Thus, if the EIA-

encoder signal leads the EIB-signal (and therefore the A signal

leads the B signal), the quadrature counter is incremented on

each edge. This (A signal leads the B signal) is defined as the

forward direction of motion. Setting Bit 0 of the EIUCTRL regis-

ter causes the signal at the EIA pin to be fed to the B input to

the quadrature counter and the signal EIB becomes the A input

to the quadrature counter. Therefore, if the EIA signal led the

EIB signal at the pins of the ADMC401, the A input to the

quadrature counter will now lag the B input. This will be recog-

nized as rotation in the reverse direction and the counter will be

decremented on each quadrature pulse. Following a reset, the

REV bit is cleared.

The two encoder signals are used to derive a quadrature signal

that is used, in conjunction with a direction bit, to increment or

decrement the encoder counter and also the encoder event

timer. The status of the direction signal is indicated at Bit 1

of the EIUSTAT register. While the encoder counter is incre-

menting, Bit 1 is set. Alternatively, when the encoder counter

is decrementing, Bit 1 of the EIUSTAT register is cleared.

Alternative Frequency and Direction Inputs

Instead of the quadrature EIA and EIB encoder inputs, the

encoder interface unit can also accept alternative Frequency and

Direction Inputs. This mode is enabled by setting Bit 6 of the

EIUCTRL register. In this so-called FD Mode, the EIA input

pin accepts a frequency signal and the EIB pin accepts the di-

rection signal. The signal on these pins are subject to the same

synchronization and filtering logic as described previously. How-

ever, in this mode the quadrature counter is incremented or

decremented on both the falling and rising edges of the signal

on the EIA pin. If the EIB pin is LO, forward operation is as-

sumed and the counter is incremented on each edge of the fre-

quency signal on the EIA input. On the other hand, if the EIB

pin is HI, reverse rotation is assumed and the quadrature

counter is decremented at each edge of the signal on the EIA

pin. On power-up or reset, Bit 6 of the EIUCTRL register is

cleared so that this mode is disabled by default. The following

modes are not supported when FD Mode is enabled: Encoder

Counter Reset mode, Single North Marker mode, and Encoder

Error Checking mode. In other words, when Bit 6 of EIUCTRL

is set, Bits 1, 2, and 3 should be cleared.

Encoder Counter Reset

The ZERO bit (Bit 1) of the EIUCTRL register determines if

the encoder zero marker is used to hardware reset the up/down

counter of the encoder interface. When Bit 1 of the EIUCTRL

reset the up/down counter to zero (if moving in the forward

direction) or to the value in the EIUMAXCNT register (if mov-

ing in the reverse direction). The reset operation takes place on

the next quadrature pulse after the zero marker has been recog-

nized. In order to ensure correct encoder counting (no missing

or spurious codes) the logic in the encoder counter latches the

conditions (appropriate encoder edge) at which the first reset is

performed. Thereafter, irrespective of operating conditions, the

encoder reset operation is always aligned with the same encoder

edge. For example, if the first reset operation occurs on the

rising edge of B and the encoder is moving in the forward direc-

tion, then all subsequent reset operations are aligned with the

rising edge of the B signal (while moving in the forward direc-

tion) and on the falling edge of B for rotation in the reverse

direction. In order to account for zero marker signals of differ-

ent widths, the zero marker will be recognized as the rising edge

of the EIZ signal when moving in the forward direction. When

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