ADMC401BST datasheet(17/60 Pages) AD

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ADMC401

–17–

REV. B

PIN FUNCTION DESCRIPTION

The ADMC401 is available in an 144-lead TQFP package. Table

I contains the pin descriptions.

Table I. Pin List

Group

Input/

Name

Pins Output Function

A13–A0

Address Lines

D23–D0

I/O

Data Lines

PMS, DMS, BMS 3

External Memory Select Lines

RD, WR

External Memory Read/Write Enable

MMAP

Memory Map Select

POR

Internal Power On Reset Output

RESET

Processor Reset Input

CLKOUT

Processor Clock Output

CLKIN, XTAL

I, O

External Clock or Quartz Crystal

Input

Bus Request

BG, BGH

Bus Grant and Bus Hang Control

BMODE

Boot Mode Select

PWD, PWDACK

I, O

Power-Down and Power-Down

Acknowledge

SPORT0

I/O

Serial Port 0 Pins (TFS0, RFS0,

DT0, DR0, SCLK0)

SPORT1

I/O

Serial Port 1 (TFS1/

IRQ1, RFS1/

IRQ0/SROM, DT1/FO, DR1A/FI,

DR1B/FI, SCLK1)

VIN0–VIN7

Analog Inputs

ASHAN, BSHAN

Inverting Inputs to Sample and

Hold Amplifiers

GAIN

Analog Input for Gain Calibration

VREF

I/O

Reference Voltage Input/Output

REFCOM

GND

Reference Common

CML

Common-

Mode Level (Midsupply)

CAPT, CAPB

Noise Reduction Pins

SENSE

Voltage Reference Select

CONVST

External Convert Start

AH-CL

PWM Outputs

PWMTRIP

PWM Shutdown Signal

PWMPOL

PWM Polarity Control

PWMSYNC

PWM Synchronization Output

PWMSR

PWM Switched Reluctance Mode

Control

PIO0–PIO11

I/O

Digital I/O Port

ETU0, ETU1

Event Timer Inputs

AUX0–AUX1

Auxiliary PWM Outputs

EIA, EIB, EIZ,

EIS

Encoder Interface Inputs and

External Registration Inputs

No Connect

AVDD

SUP

Analog Power Supply

AVSS

GND

Analog Ground

VDD

SUP

Digital Power Supply

GND

Digital Ground

INTERRUPT OVERVIEW

The ADMC401 can respond to different interrupt sources, some

of which are internal DSP core interrupts and others from the

motor control peripherals. The DSP core interrupts include a:

•

Power up (or

RESET) interrupt.

•

A peripheral (or

IRQ2) interrupt.

•

A SPORT0 receive and a SPORT0 transmit interrupt.

•

A SPORT1 receive (or

IRQ0) and a SPORT1 transmit (or

IRQ1) interrupt.

•

Two software interrupts.

•

An interval timer timeout interrupt.

•

A power-down interrupt.

In addition, the motor control peripherals add other interrupts

that include:

• A PWMSYNC interrupt.

• An ADC end of conversion interrupt.

• An encoder loop timer timeout interrupt.

• Five peripheral input/output (PIO) interrupts.

• An event timer interrupt.

• An encoder count error interrupt.

• A PWM trip interrupt.

The interrupts are internally prioritized and individually maskable

except for the nonmaskable power-down interrupt.

Memory Map

The ADMC401 has two distinct memory types; program memory

and data memory (in addition to external boot memory). In

general, program memory contains user code and coefficients,

while the data memory is used to store variables and data during

program execution. Both program memory RAM and ROM is

provided internally on the ADMC401. The program memory

map of the ADMC401 can be altered depending on the state of

the MMAP and BMODE pins. The various program memory

maps are illustrated in Figure 11 for the permissible settings of

MMAP and BMODE. The state of these pins also impact the

way in which the internal memory of the ADMC401 is booted,

as described later.

There is 2K of internal ROM on the ADMC401. Setting the

ROMENABLE bit on the Data Memory Wait State Control

ROMENABLE bit is set to 1, addressing program memory in the

ROM range will access the on-chip ROM. When ROMENABLE

is set to zero, addressing program memory in this range will

access external program memory. The ROMENABLE bit is

initialized to zero after reset unless MMAP and BMODE = 1.

When MMAP = BMODE = 0, the ADMC401 provides 2K

× 24

bits of internal program memory RAM starting at address

0x0000 that is booted from a byte-wide interface on the address

and data buses. Following boot loading, program execution

starts at address 0x0000. In this mode, the remainder of the

program memory space, a 12K

× 24-bit block starting at address

0x1000, is assigned to external memory.

When MMAP = BMODE = 1, the program memory map is

identical to the previous case, but ROMENABLE defaults to 1 at

reset, and execution starts from the internal program memory

ROM located at address 0x0800. This permits the internal (and

external if desired) memory to be boot loaded across the various

serial interfaces on SPORT1.

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