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AD9887

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DIGITAL INTERFACE PIN DESCRIPTIONS

Digital Video Data Inputs

Rx0+

Positive Differential Input Video Data (Channel 0)

Rx0–

Negative Differential Input Video Data (Channel 0)

Rx1+

Positive Differential Input Video Data (Channel 1)

Rx1–

Negative Differential Input Video Data (Channel 1)

Rx2+

Positive Differential Input Video Data (Channel 2)

Rx2–

Negative Differential Input Video Data (Channel 2)

These six pins receive three pairs of differential,

low voltage swing input pixel data from a digital

graphics transmitter.

Digital Video Clock Inputs

RxC+

Positive Differential Input Video Clock

RxC–

Negative Differential Input Video Clock

These two pins receive the differential, low voltage

swing input pixel clock from a digital graphics

transmitter.

Termination Control

RTERM

Internal Termination Set Pin

This pin is used to set the termination resistance

for all of the digital interface high-speed inputs. To

set, place a resistor of value equal to 10

× the desired

input termination resistance between this pin (Pin

53) and ground supply. Typically, the value of this

resistor should be 500

Ω.

Outputs

Data Enable Output

This pin outputs the state of data enable, (DE).

The AD9887 decodes DE from the incoming

stream of data. The DE signal will be HIGH dur-

ing active video and will be LOW while there is no

active video.

Power Supply

Main Power Supply

It should be as quiet and as ﬁltered as possible.

PVD

PLL Power Supply

It should be as quiet and as ﬁltered as possible.

VDD

Outputs Power Supply

The power for the data and clock outputs. It can

run at 3.3 V or 2.5 V.

THEORY OF OPERATION (DIGITAL INTERFACE)

Capturing of the Encoded Data

The ﬁrst step in recovering the encoded data is to capture the

raw data. To accomplish this, the AD9887 employs a high-speed

Phase Locked Loop (PLL), to generate clocks capable of

oversampling the data at the correct frequencies. The data

capture circuitry continuously monitors the incoming data during

horizontal and vertical blanking times (when DE is low), and

independently selects the best sampling phase for each data

channel. The phase information is stored and used until the next

blanking period (one video line).

Data Frames

The digital interface data is captured in groups of 10 bits each,

called a data frame. During the active data period, each frame is

made up the nine encoded video data bits and one dc balancing

bit. The data capture block receives this data serially, but out-

puts each frame in parallel 10-bit words.

Special Characters

During periods of horizontal or vertical blanking time (when

DE is low), the digital transmitter will transmit special characters.

The AD9887 will receive these characters and use them to set the

video frame boundaries and the phase recovery loop for each

channel. There are four special characters that can be received.

They are used to identify the top, bottom, left side, and right side

of each video frame. The data receiver can differentiate these

special characters from active data because the special characters

have a different number of transitions per data frame.

Channel Resynchronization

The purpose of the channel resynchronization block is to resyn-

chronize the three data channels to a single internal data clock.

Coming into this block, all three data channels can be on differ-

ent phases of the three times oversampling PLL clock (0

°, 120°,

and 240

°). This block can resynchronize the channels from a

worst-case skew of one full input period (8.93 ns at 112 MHz).

Data Decoder

The data decoder receives frames of data and sync signals from

the data capture block (in 10-bit parallel words), and decodes

them into groups of eight RGB/YUV bits, two control bits, and

a data enable bit (DE).

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