AD9887SLASHPCB datasheet(37/40 Pages) AD

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AD9887

–37–

Write to four consecutive control registers

➥Start signal

➥Slave Address byte (R/W bit = LOW)

➥Base Address byte

➥Data byte to base address

➥Data byte to (base address + 1)

➥Data byte to (base address + 2)

➥Data byte to (base address + 3)

➥Stop signal

Read from one control register

➥Start signal

➥Slave Address byte (R/W bit = LOW)

➥Base Address byte

➥Start signal

➥Slave Address byte (R/W bit = HIGH)

➥Data byte from base address

➥Stop signal

Read from four consecutive control registers

➥Start signal

➥Slave Address byte (R/W bit = LOW)

➥Base Address byte

➥Start signal

➥Slave Address byte (R/W bit = HIGH)

➥Data byte from base address

➥Data byte from (base address + 1)

➥Data byte from (base address + 2)

➥Data byte from (base address + 3)

➥Stop signal

BIT 7

SDA

SCL

ACK

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Figure 37. Serial Interface—Typical Byte Transfer

Table LIV. Control of the Sync Block Muxes via the

Serial Register

Control

Mux

Serial Bus

Bit

Nos.

Control Bit

State

Result

1 and 2

12H: Bit 4

Pass Hsync

Pass Sync-on-Green

12H: Bit 1

Pass Coast

Pass Vsync

12H: Bit 2

Pass Vsync

Pass Sync Separator Signal

5, 6, and 7 11H: Bit 3

Pass Digital Interface Signals

Pass Analog Interface Signals

THEORY OF OPERATION (SYNC PROCESSING)

This section is devoted to the basic operation of the sync process-

ing engine (refer to Figure 37 Sync Processing Block Diagram).

Sync Slicer

The purpose of the sync slicer is to extract the sync signal from

the green graphics channel. A sync signal is not present on all

graphics systems, only those with “sync-on-green.” The sync

signal is extracted from the green channel in a two step process.

First, the SOG input is clamped to its negative peak (typically

0.3 V below the black level). Next, the signal goes to a compara-

tor with a trigger level that is 0.15 V above the clamped level.

The “sliced” sync is typically a composite sync signal containing

both Hsync and Vsync.

Sync Separator

A sync separator extracts the Vsync signal from a composite

sync signal. It does this through a low-pass ﬁlter-like or integrator-

like operation. It works on the idea that the Vsync signal stays

active for a much longer time than the Hsync signal, so it rejects

any signal shorter than a threshold value, which is somewhere

between an Hsync pulsewidth and a Vsync pulsewidth.

The sync separator on the AD9887 is simply an 8-bit digital

counter with a 5 MHz clock. It works independently of the

polarity of the composite sync signal. (Polarities are determined

elsewhere on the chip.) The basic idea is that the counter counts

up when Hsync pulses are present. But since Hsync pulses are

relatively short in width, the counter only reaches a value of N

before the pulse ends. It then starts counting down eventually

reaching 0 before the next Hsync pulse arrives. The speciﬁc

value of N will vary for different video modes, but will always be

less than 255. For example with a 1

µs width Hsync, the counter

will only reach 5 (1

µs/200 ns = 5). Now, when Vsync is present

on the composite sync the counter will also count up. However,

since the Vsync signal is much longer, it will count to a higher

number M. For most video modes, M will be at least 255. So,

Vsync can be detected on the composite sync signal by detecting

when the counter counts to higher than N. The speciﬁc count

that triggers detection (T) can be programmed through the

serial register (0fh).

Once Vsync has been detected, there is a similar process to detect

when it goes inactive. At detection, the counter ﬁrst resets to 0,

then starts counting up when Vsync goes away. Similar to the

previous case, it will detect the absence of Vsync when the

counter reaches the threshold count (T). In this way, it will

reject noise and/or serration pulses. Once Vsync is detected to

be absent, the counter resets to 0 and begins the cycle again.

SDA

SCL

tBUFF

tSTAH

tDHO

tDSU

tDAL

tDAH

tSTASU

tSTOSU

Figure 36. Serial Port Read/

Write Timing

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