AD9887SLASHPCB datasheet(35/40 Pages) AD

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AD9887

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DIGITAL CONTROL

7:0

Sync Separator Threshold

This register is used to set the responsiveness of the sync

separator. It sets how many pixel clock pulses the sync

separator must count to before toggling high or low. It

works like a low-pass ﬁlter to ignore Hsync pulses in order

to extract the Vsync signal. This register should be set to

some number greater than the maximum Hsync pulsewidth.

The default for this register is 32.

CONTROL BITS

Scan Enable

This register is used to enable the scan function. When

enabled, data can be loaded into the AD9887 outputs

serially with the scan function. The scan function utilizes

three pins (SCANIN, SCANOUT, and SCANCLK). These

pins are described in Table I.

Table XLV. Scan Enable Settings

Scan Enable

Result

Scan Function Disabled

Scan Function Enabled

The default for scan enable is 0 (disabled).

Coast Input Polarity Override

This register is used to override the internal circuitry that

determines the polarity of the coast signal going into

the PLL.

Table XLVI. Coast Input Polarity Override Settings

Override Bit

Result

Coast Polarity Determined by Chip

Coast Polarity Determined by User

The default for coast polarity override is 0 (polarity

determined by chip).

HSYNC Input Polarity Override

This register is used to override the internal circuitry that

determines the polarity of the Hsync signal going into

the PLL.

Table XLVII. HSYNC Input Polarity Override Settings

Override Bit

Result

Hsync Polarity Determined by Chip

Hsync Polarity Determined by User

The default for Hsync polarity override is 0 (polarity

determined by chip).

HSYNC Input Polarity Status

This bit reports the status of the Hsync input polarity

detection circuit. It can be used to determine the polarity

of the Hsync input. The detection circuit’s location is

shown in the Sync Processing Block Diagram (Figure 38).

Table XLVIII. Detected HSYNC Input Polarity Status

Hsync Polarity

Status

Result

Hsync Polarity is Negative.

Hsync Polarity is Positive.

VSYNC Output Polarity Status

This bit reports the status of the Vsync output polarity

detection circuit. It can be used to determine the polarity

of the Vsync input. The detection circuit’s location is

shown in the Sync Processing Block Diagram (Figure 38).

Table XLIX. Detected VSYNC Input Polarity Status

Vsync Polarity

Status

Result

Vsync Polarity is Active Low.

Vsync Polarity is Active High.

Coast Input Polarity Status

This bit reports the status of the coast input polarity

detection circuit. It can be used to determine the polar-

ity of the coast input. The detection circuit’s location is

shown in the Sync Processing Block Diagram (Figure 38).

Table L. Detected Coast Input Polarity Status

Coast Polarity

Status

Result

Coast Polarity is Negative.

Coast Polarity is Positive.

7–3

Sync-on-Green Slicer Threshold

This register allows the comparator threshold of the

Sync-on-Green slicer to be adjusted. This register adjusts

the comparator threshold in steps of 10 mV. A setting of zero

results in a 330 mV threshold. The setting of 31 results in

a 10 mV threshold.

The default setting is 23 and corresponds to a threshold

value of 70 mV.

7–0

Pre-Coast

This register allows the Coast signal to be applied prior

to the Vsync signal. This is necessary in cases where pre-

equalization pulses are present. The step size for this

control is one Hsync period.

The default is 0.

7–0

Post-Coast

This register allows the coast signal to be applied follow-

ing to the Vsync signal. This is necessary in cases where

post-equalization pulses are present. The step size for this

control is one Hsync period.

The default is 0.

7–0

Test Register

Must be set to default.

7–0

Test Register

Must be set to 41H for proper operation.

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