AD9887SLASHPCB datasheet(38/40 Pages) AD

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AD9887

PCB LAYOUT RECOMMENDATIONS

The AD9887 is a high-performance, high-speed analog device.

As such, to get the maximum performance out of the part it is

important to have a well laid-out board. The following is a guide

for designing a board using the AD9887.

Analog Interface Inputs

Using the following layout techniques on the graphics inputs is

extremely important:

Minimize the trace length running into the graphics inputs. This

is accomplished by placing the AD9887 as close as possible to

the graphics VGA connector. Long input trace lengths are unde-

sirable because they will pick up more noise from the board and

other external sources.

Place the 75

Ω termination resistors as close to the AD9887

chip as possible. Any additional trace length between the termi-

nation resistors and the input of the AD9887 increases the

magnitude of reflections, which will corrupt the graphics signal.

Use 75

Ω matched impedance traces. Trace impedances other

than 75

Ω will also increase the chance of reflections.

The AD9887 has very high input bandwidth, (330 MHz). While

this is desirable for acquiring a high resolution PC graphics

signal with fast edges, it means that it will also capture any high

frequency noise present. Therefore, it is important to reduce the

amount of noise that gets coupled to the inputs. Avoid running

any digital traces near the analog inputs.

Due to the high bandwidth of the AD9887, sometimes low-pass

ﬁltering the analog inputs can help to reduce noise. (For many

applications, ﬁltering is unnecessary.) Experiments have shown

that placing a series ferrite bead prior to the 75

Ω termination

resistor is helpful in ﬁltering out excess noise. Speciﬁcally, the

part used was the # 2508051217Z0 from Fair-Rite, but each

application may work best with a different bead value. Alternately,

placing a 100

Ω to 120 Ω resistor between the 75 Ω termination

resistor and the input coupling capacitor can also be beneficial.

Digital Interface Inputs

Each differential input pair (RXO+, RXO–, RXC+, RXC–, etc.)

should be routed together using 50

Ω strip line routing tech-

niques and should be kept as short as possible. No other

components should be placed on these inputs; for example, no

clamping diodes. Every effort should also be made to route

these signals on a single layer (component layer) with no vias.

Power Supply Bypassing

It is recommended to bypass each power supply pin with a

0.1

µF capacitor. The exception is in the case where two or

more supply pins are adjacent to each other. For these group-

ings of powers/grounds, it is only necessary to have one bypass

capacitor. The fundamental idea is to have a bypass capacitor

within about 0.5 cm of each power pin. Also, avoid placing the

capacitor on the opposite side of the PC board from the AD9887,

as that interposes resistive vias in the path.

The bypass capacitors should be physically located between the

power plane and the power pin. Current should flow from the

power plane to the capacitor to the power pin. Do not make the

power connection between the capacitor and the power pin.

Placing a via underneath the capacitor pads, down to the power

plane, is generally the best approach.

SYNC STRIPPER

ACTIVITY

DETECT

NEGATIVE PEAK

CLAMP

COMP

SYNC

SOG

HSYNC IN

ACTIVITY

DETECT

MUX 2

HSYNC OUT

PIXEL CLOCK

MUX 1

SYNC SEPARATOR

INTEGRATOR

VSYNC

SOG OUT

HSYNC OUT

VSYNC OUT

MUX 4

VSYNC IN

1/S

PLL

HSYNC

ACTIVITY

DETECT

AD9887

CLOCK

GENERATOR

POLARITY

DETECT

POLARITY

DETECT

POLARITY

DETECT

MUX 3

COAST

Figure 38. Sync Processing Block Diagram

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