AD9887SLASHPCB datasheet(12/40 Pages) AD

12 / 40 page

REV. 0

–12–

AD9887

Table III. Interface Selection Controls

Analog

Digital

Active

AIO

Interface Detect

AIS

Interface

Description

Analog

Force the analog interface active.

Digital

Force the digital interface active.

None

Neither interface was detected. Both interfaces are

powered down and the SyncDT pin gets set to Logic 0.

Digital

The digital interface was detected. Power down the

analog interface.

Analog

The analog interface was detected. Power down the

digital interface.

Analog

Both interfaces were detected. The analog interface has

priority.

Digital

Both interfaces were detected. The digital interface has

priority.

Table IV. Power-Down Mode Descriptions

Inputs

Analog

Digital

Active

Power-

Interface

Mode

Down

Detect

Override

Select

Powered On or Comments

Soft Power-Down (Seek Mode)

Serial Bus, Digital Interface Clock Detect,

Analog Interface Activity Detect, SOG,

Bandgap Reference

Digital Interface On

Serial Bus, Digital Interface, Analog Interface

Activity Detect, SOG, Outputs, Bandgap

Reference

Analog Interface On

Serial Bus, Analog Interface, Digital Interface

Clock Detect, SOG, Outputs, Bandgap

Reference

Serial Bus Arbitrated Interface

Same as Analog Interface On Mode

Serial Bus Arbitrated Interface

Same as Digital Interface On Mode

Override to Analog Interface

Same as Analog Interface On Mode

Override to Digital Interface

Same as Digital Interface On Mode

Absolute Power-Down

Serial Bus

NOTES

1Power-down is controlled via bit 0 in serial bus Register 12h.

2Analog Interface Detect is determined by OR-ing Bits 7, 6, and 5 in serial bus Register 11h.

3Digital Interface Detect is determined by Bit 4 in serial bus Register 11h.

Power Management

The AD9887 is a dual interface device with shared outputs.

Only one interface can be used at a time. For this reason, the

chip automatically powers down the unused interface. When

the analog interface is being used, most of the digital interface

circuitry is powered down and vice-versa. This helps to minimize

the AD9887 total power dissipation. In addition, if neither inter-

face has activity on it, the chip powers down both interfaces.

The AD9887 uses the activity detect circuits, the active inter-

face bits in the serial registers, the active interface override bits,

and the power-down bit to determine the correct power state.

In a given power mode not all circuitry in the inactive interface

is powered down completely. When the digital interface is

active, the bandgap reference and HSYNC detect circuitry is not

powered down. When the analog interface is active, the digital

interface clock detect circuit is not powered down. Table IV

summarizes how the AD9887 determines which power mode to

be in and what circuitry is powered on/off in each of these

modes. The power-down command has priority, followed by the

active interface override, and then the automatic circuitry.

AD9887/PCB датащи(PDF) 12 Page - Analog Devices

AD9887/PCB датащи(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

датащи скачать

ссылки URL