WM8311 datasheet(65/302 Pages) WOLFSON

65 / 302 page

Pre-Production

WM8311

PP, May 2012, Rev 3.1

Note that OTP_CMD_END_EINT is triggered during the normal start-up and shutdown operations,

when the WM8311 accesses the OTP and/or ICE memories. For typical applications, it is

recommended that the OTP_CMD_END_EINT interrupt should be masked at all times except when

performing user-initiated OTP/DBE commands.

ADDRESS

BIT

LABEL

DESCRIPTION

R16402

(4012h)

Interrupt Status

OTP_CMD_END_EINT

OTP / ICE Command End interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

OTP_ERR_EINT

OTP / ICE Command Fail interrupt

(Rising Edge triggered)

Note: Cleared when a ‘1’ is written.

R16410

(401Ah)

Interrupt Status

2 Mask

IM_OTP_CMD_END_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

IM_OTP_ERR_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 28 OTP Memory Interrupts

14.6 DCRW MEMORY CONTENTS

The DCRW is the ICE/OTP Register Window, as described in Section 14.2. Under normal operating

conditions, this memory area is initialised with data from the integrated OTP or an external ICE

memory. The DCRW memory addresses range from R30720 (7800h) to R30759 (7827h). The

complete register map definition is described in Section 28.

The register fields in the DCRW allow the start-up configuration of the DC-DC Converters, the LDO

Regulators, GPIO pins 1-6 and Status LED outputs to be programmed. The DCRW also provides

control of the Battery Charger, Clocking, USB Current Limit and the Start-Up (SYSOK) voltage

threshold.

Most of the DCRW contents are duplicates of control registers that exist in the main register area

below the DCRW addresses. In theses cases, reading or writing to either address will have the same

effect.

Some register fields are defined only in the DCRW area; a detailed description of these fields is

provided in the following sub-sections.

14.6.1 DCRW PAGE 0

Page 0 of the DCRW occupies register addresses R30720 (7800h) to R30727 (7807h). This contains

factory-preset data which is loaded from OTP when an ‘ON’ state transition is scheduled.

Page 0 of the DCRW contains a 128-bit unique ID. Note that these fields are Read-Only in the OTP

and cannot be changed.

14.6.2 DCRW PAGE 1

Page 1 of the DCRW occupies register addresses R30728 (7808h) to R30735 (780Fh). This contains

factory-preset data which is loaded from OTP when an ‘ON’ state transition is scheduled.

Page 1 of the DCRW contains trim parameters that ensure the accuracy of the voltage references

and the power management RC oscillator. Note that these fields are Read-Only in the OTP and

cannot be changed.

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