WM8311 datasheet(42/302 Pages) WOLFSON

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WM8311

Pre-Production

PP, May 2012, Rev 3.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

1:0

ON_PIN_TO

¯¯ pin timeout period

00 = 1s

01 = 2s

10 = 4s

11 = 8s

Protected by user key

Table 5 ON Pin Control Registers

The ON

¯¯ pin interrupt event is always raised as part of the primary action when the ON

¯¯ pin is asserted.

The ON

¯¯ pin interrupt is a selectable option as the secondary action. The ON

¯¯ pin interrupt event is also

raised when the ON

¯¯ pin is de-asserted.

The ON

¯¯ pin interrupt event is indicated by the ON_PIN_CINT register field. This secondary interrupt

triggers a primary ON Pin Interrupt, ON_PIN_INT (see Section 23). This can be masked by setting the

mask bit as described in Table 6.

ADDRESS

BIT

LABEL

DESCRIPTION

R16401

(4011h)

Interrupt Status

ON_PIN_CINT

ON pin interrupt.

(Rising and Falling Edge triggered)

Note: Cleared when a ‘1’ is written.

R16409

(4019h)

Interrupt Status

1 Mask

IM_ON_PIN_CINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 6 ON Pin Interrupt

11.7 RESET PIN FUNCTION

The RESET

¯¯¯¯¯¯ pin is an active low input/output which is used to command Hardware Resets in the

WM8311 and in other connected devices. The pin is an open-drain type, with integrated pull-up; it can

be driven low by external sources or by the WM8311 itself.

The WM8311 drives the RESET

¯¯¯¯¯¯ pin low in the OFF state. The output status of the RESET

¯¯¯¯¯¯ pin in

SLEEP is configurable; this is determined by the RST_SLPENA register bit as defined in Table 7.

The WM8311 clears the RESET

¯¯¯¯¯¯ pin following the transition to ON. On completion of the state

transition, the RESET

¯¯¯¯¯¯ pin is held low for a further delay time period, extending the RESET

¯¯¯¯¯¯ low

duration. The RESET

¯¯¯¯¯¯ delay period is set by the RST_DUR register bit. See Figure 6 for further

details.

The WM8311 detects a Hardware Reset request whenever the RESET

¯¯¯¯¯¯ pin is driven low by an

external source. In this event, the WM8311 resets the internal control registers (excluding the RTC)

and initiates a start-up sequence. See Section 24.

It is possible to mask the RESET

¯¯¯¯¯¯ pin input in the SLEEP state by setting the RST_SLP_MSK register

bit. In SLEEP mode, if RST_SLP_MSK is set, the WM8311 will take no action if the RESET

¯¯¯¯¯¯ pin is

pulled low.

Note that the RESET

¯¯¯¯¯¯ pin control registers are locked by the WM8311 User Key. These registers can

only be changed by writing the appropriate code to the Security register, as described in Section 12.4.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R16390 (4006h)

Reset Control

RST_SLP_MSK

Masks the RESET

¯¯¯¯¯¯ pin input in

SLEEP mode

0 = External RESET

¯¯¯¯¯¯ active in SLEEP

1 = External RESET

¯¯¯¯¯¯ masked in

SLEEP

Protected by user key

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