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WM8311 датащи(PDF) 55 Page - Wolfson Microelectronics plc |
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WM8311 датащи(HTML) 55 Page - Wolfson Microelectronics plc |
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55 / 302 page ![]() Pre-Production WM8311 w PP, May 2012, Rev 3.1 55 ADDRESS BIT LABEL DEFAULT DESCRIPTION 2:0 FLL_FRATIO [2:0] 000 FVCO clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1XX = 16 000 recommended for high FREF 011 recommended for low FREF R16532 (4094h) FLL Control 3 15:0 FLL_K [15:0] 0000h Fractional multiply for FREF (MSB = 0.5) R16533 (4095h) FLL Control 4 14:5 FLL_N [9:0] 177h Integer multiply for FREF (LSB = 1) 3:0 FLL_GAIN [3:0] 0000 Gain applied to error 0000 = x 1 (Recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1XXX = x 256 Recommended that this register is not changed from default. R16534 (4096h) FLL Control 5 4:3 FLL_CLK_RE F_DIV [1:0] 00 FLL Clock Reference Divider 00 = 1 01 = 2 10 = 4 11 = 8 CLKIN must be divided down to <=13.5MHz. For lower power operation, the reference clock can be divided down further if desired. 1:0 FLL_CLK_SR C [1:0] 00 FLL Clock source 00 = 32.768kHz xtal oscillator 01 = CLKIN 10 = Reserved 11 = Reserved Table 20 FLL Control |
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