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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TUSB7320 датащи(PDF) 68 Page - Texas Instruments |
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TUSB7320 датащи(HTML) 68 Page - Texas Instruments |
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68 / 115 page  TUSB7320, TUSB7340 SLLSE76J – MARCH 2011 – REVISED MAY 2012 www.ti.com Table 5-7. Bit Descriptions – Uncorrectable Error Mask Register(1) (continued) Flow Control Error Mask. 13† FC_ERROR_MASK † rw 0 – Error Condition is Unmasked 1 – Error Condition is Masked Poisoned TLP Mask. 12† PSN_TLP_MASK † rw 0 – Error Condition is Unmasked 1 – Error Condition is Masked 11:5 RSVD r Reserved. Returns zeros when read. Data Link Protocol Error Mask. 4† DLL_ERROR_MASK † rw 0 – Error Condition is Unmasked 1 – Error Condition is Masked 3:0 RSVD r Reserved. Returns zeros when read. 5.6 Uncorrectable Error Severity Register The Uncorrectable Error Severity Register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition will be identified as fatal. When a bit is clear, the corresponding error condition will be identified as non-fatal. PCI Express Extended Register Offset: 10Ch Register type:Read-Only, Read/Write Default value: 0026 2030h Table 5-8. PCI Express Extended Register 10Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 No. Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 State Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No. Reset 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 State Table 5-9. Bit Descriptions – Uncorrectable Error Severity Register(1) Bit Field Name Access Description 31:23 RSVD r Reserved. Returns zeros when read. 22 RSVD r Reserved. Returns ‘1’ when read. 21 RSVD r Reserved. Returns zeros when read. Unsupported Request Error Severity. 20† UR_ERROR_SEVR † rw 0 – Error Condition is signaled using ERR_NONFATAL 1 – Error Condition is signaled using ERR_FATAL Extended CRC Error Severity. 19† ECRC_ERROR_SEVR † rw 0 – Error Condition is signaled using ERR_NONFATAL 1 – Error Condition is signaled using ERR_FATAL Malformed TLP Severity. 18† MAL_TLP_SEVR † rw 0 – Error Condition is signaled using ERR_NONFATAL 1 – Error Condition is signaled using ERR_FATAL Receiver Overflow Severity. 17† RX_OVERFLOW_SEVR † rw 0 – Error Condition is signaled using ERR_NONFATAL 1 – Error Condition is signaled using ERR_FATAL Unexpected Completion Severity. 16† UNXP_CPL_SEVR † rw 0 – Error Condition is signaled using ERR_NONFATAL 1 – Error Condition is signaled using ERR_FATAL (1) Bits marked with † are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset 68 PCI EXPRESS EXTENDED CONFIGURATION SPACE Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 |
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