TUSB7320 datasheet(55/115 Pages) TI1

55 / 115 page

TUSB7320, TUSB7340

www.ti.com

SLLSE76J – MARCH 2011 – REVISED MAY 2012

4.55 MSI-X Capability ID Register

This read-only register identifies the linked list item as the register for MSI-X Capabilities. The register

returns 11h when read.

PCI register offset: C0h

Default value: 11h

Table 4-83. PCI Register C0h

Bit No.

Reset State

4.56 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the

TUSB73X0. This register reads 00h indicating that no additional capabilities are supported.

PCI register offset: C1h

Default value: 11h

Table 4-84. PCI Register C1h

Bit No.

Reset State

4.57 MSI-X Message Control Register

This register is used to control the sending of MSI-X messages.

PCI register offset: C2h

Default value: 0007h

Table 4-85. PCI Register C2h

Bit

No.

Reset

State

Table 4-86. MSI-X Message Control Register Description

Bit

Field Name

Access

Description

MSIX_EN

MSI-X Enable.

FUNC_MASK

Function Mask.

13:11

RSVD

Reserved. Returns zero when read.

MSI-X Table Size. This field is set to 07h to indicate a table size of 8

10:0

TABLE_SIZE

entries.

CLASSIC PCI CONFIGURATION SPACE

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