TUSB7320 datasheet(49/115 Pages) TI1

49 / 115 page

TUSB7320, TUSB7340

www.ti.com

SLLSE76J – MARCH 2011 – REVISED MAY 2012

Table 4-62. Link Control Register Description (continued)

Active State Link PM Control. This field is used to enable and disable

active state PM.

00 – Active State PM Disabled

1:0

ASLPMC

01 – L0s Entry Enabled

10 – L1 Entry Enabled

11 – L0s and L1 Entry Enable

4.44 Link Status Register

The Link Status Register indicates current state of the PCI Express Link.

PCI register offset: 82h

Default value: 101xh

Table 4-63. PCI Register 82h

Bit

No.

Reset

State

Table 4-64. Link Status Register Description

Bit

Field Name

Access

Description

Link Autonomous Bandwidth Status. This bit has no function and is read

LINK_ABS

only zero.

Link Bandwidth Management Status. This bit has no function and is read

LINK_BMS

only zero.

DLL_ACTIVE

Data Link Layer Active. This bit has no function and is read only zero.

Slot Clock Configuration. This bit is ‘1’, since the TUSB73X0 uses the

SCC

100-MHz differential reference clock provided by the platform.

Link Training. This bit has no function and is read only zero.

Retrain Link. This bit has no function and is read only zero.

Negotiated Link Width. This field is read only 000001b indicating the lane

9:4

NLW

width is 1x.

3:0

Link Speed. This field indicates the negotiated link speed.

4.45 Device Capabilities 2 Register

The Device Capabilities 2 Register indicates the device specific capabilities of the TUSB73X0.

PCI register offset: 94h

Default value: 0000 0010h

CLASSIC PCI CONFIGURATION SPACE

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