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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TUSB7320 датащи(PDF) 3 Page - Texas Instruments |
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TUSB7320 датащи(HTML) 3 Page - Texas Instruments |
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3 / 115 page  TUSB7320, TUSB7340 www.ti.com SLLSE76J – MARCH 2011 – REVISED MAY 2012 4.31 MSI Lower Message Address Register ................................................................................. 41 4.32 MSI Upper Message Address Register ................................................................................. 42 4.33 MSI Message Data Register ............................................................................................. 42 4.34 Serial Bus Release Number Register (SBRN) ........................................................................ 43 4.35 Frame Length Adjustment Register (FLADJ) .......................................................................... 43 4.36 PCI Express Capability ID Register ..................................................................................... 43 4.37 Next Item Pointer Register ............................................................................................... 44 4.38 PCI Express Capabilities Register ...................................................................................... 44 4.39 Device Capabilities Register ............................................................................................. 45 4.40 Device Control Register .................................................................................................. 46 4.41 Device Status Register ................................................................................................... 47 4.42 Link Capabilities Register ................................................................................................ 47 4.43 Link Control Register ...................................................................................................... 48 4.44 Link Status Register ....................................................................................................... 49 4.45 Device Capabilities 2 Register ........................................................................................... 49 4.46 Device Control 2 Register ................................................................................................ 50 4.47 Link Control 2 Register ................................................................................................... 50 4.48 Link Status 2 Register .................................................................................................... 51 4.49 Serial Bus Data Register ................................................................................................. 51 4.50 Serial Bus Index Register ................................................................................................ 52 4.51 Serial Bus Slave Address Regsiter ..................................................................................... 52 4.52 Serial Bus Control and Status Register ................................................................................ 52 4.53 GPIO Control Register .................................................................................................... 53 4.54 GPIO Data Register ....................................................................................................... 54 4.55 MSI-X Capability ID Register ............................................................................................ 55 4.56 Next Item Pointer Register ............................................................................................... 55 4.57 MSI-X Message Control Register ....................................................................................... 55 4.58 MSI-X Table Offset and BIR Register .................................................................................. 56 4.59 MSI-X PBA Offset and BIR Register .................................................................................... 56 4.60 Subsystem Access Register ............................................................................................. 57 4.61 General Control 0 Register ............................................................................................... 57 4.62 General Control 1 Register ............................................................................................... 58 4.63 General Control 2 Register ............................................................................................... 59 4.64 USB Control Register ..................................................................................................... 59 4.65 De-Emphasis and Swing Control Register ............................................................................. 61 4.66 Equalizer Control Register ............................................................................................... 62 4.67 Custom PHY Transmit/Receive Control Register ..................................................................... 63 5 PCI EXPRESS EXTENDED CONFIGURATION SPACE ............................................................. 65 5.1 The PCI Express Extended Configuration Map ....................................................................... 65 5.2 Advanced Error Reporting capability Register ......................................................................... 65 5.3 Next Capability Offset / Capability Version Register .................................................................. 66 5.4 Uncorrectable Error Status Register .................................................................................... 66 5.5 Uncorrectable Error Mask Register ..................................................................................... 67 5.6 Uncorrectable Error Severity Register .................................................................................. 68 5.7 correctable Error Severity Register ..................................................................................... 69 5.8 correctable Error Mask Register ......................................................................................... 70 5.9 Advanced Error Capabilities and control Register .................................................................... 71 5.10 Header Log Register ...................................................................................................... 72 5.11 Device Serial Number Capability ID Register ......................................................................... 72 5.12 Next Capability Offset/Capability Version Register ................................................................... 72 5.13 Device Serial Number Register .......................................................................................... 73 6 xHCI MEMORY MAPPED REGISTER SPACE ......................................................................... 74 6.1 The xHCI Register Map ................................................................................................... 74 Copyright © 2011–2012, Texas Instruments Incorporated Contents 3 |
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