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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TUSB7320 датащи(PDF) 46 Page - Texas Instruments |
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TUSB7320 датащи(HTML) 46 Page - Texas Instruments |
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46 / 115 page  TUSB7320, TUSB7340 SLLSE76J – MARCH 2011 – REVISED MAY 2012 www.ti.com Table 4-54. Device Capabilities Register Description (continued) Max Payload Size Supported. This field indicates the maximum payload 2:0 MPSS r size that the device can support for TLPs. This field is encoded as 011b indicating the Max Payload size for a TLP is 1 Kbyte. 4.40 Device Control Register The Device Control Register controls PCI Express device specific parameters. PCI register offset: 78h Register type:Read/Write Default value: 2810h Table 4-55. PCI Register 78h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No. Reset 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 State Table 4-56. Device Control Register Description Bit Field Name Access Description Initiate Function Level Reset. A write of 1b initiates Function Level Reset 15 INITIATE_FLR rw to the Function. The value read by software from this bit is always 0b. Max Read Request Size. This field is programmed by host software to set the maximum size of a read request that the TUSB73X0 can generate. This field is encoded as: 000 – 128B 001 – 256B 14:12 MRRS rw 010 – 512B (default) 011 – 1024B 100 – 2048B101 – 4096B 110 – Reserved 111 – Reserved Enable No Snoop. Controls the setting of the “No Snoop” flag within the TLP header for upstream memory transactions mapped to any traffic class mapped to a virtual channel other than VC0 through the Upstream 11 ENS rw Decode Windows. 0 – No snoop field is ‘0’ 1 – No snoop field is ‘1’ (default) 10 APPE rw Auxiliary Power PM Enable. This bit is only reset by a Global Reset. Phantom Function Enable. Since the TUSB73X0 does not support 9 PFE r phantom functions this bit is read only zero. 8 ETFE rw Extended Tag Field Enable. 7:5 MPS rw Max Payload Size. 4 ERO rw Enable Relaxed Ordering. 3 URRE rw Unsupported Request Reporting Enable. 2 FERE rw Fatal Error Reporting Enable. 1 NFERE rw Non-Fatal Error Reporting Enable. 0 CERE rw Correctable Error Reporting Enable. 46 CLASSIC PCI CONFIGURATION SPACE Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 |
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