TFP410-EP

PanelBus

™ DIGITAL TRANSMITTER

SGLS344A − JULY 2006 − REVISED MAY 2011

8

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) − (continued)

ac specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IDCK frequency

25

165

MHz

Pixel time period (see Note 1)

6.06

40

ns

IDCK duty cycle

30%

70%

IDCK clock jitter tolerance

2

ns

t

DVI output rise time (20 80%) (see Note 2)

f

165 MHz

0°C to 70°C

75

240

ps

DVI output rise time (20-80%) (see Note 2)

−55°C to 125°C

45

320

ps

t

DVI output fall time (20 80%) (see Note 2)

f

165 MHz

0°C to 70°C

75

240

ps

DVI output fall time (20-80%) (see Note 2)

−55°C to 125°C

45

320

ps

DVI output intra-pair + to − differential skew

(see Note 3)

50

ps

DVI output inter-pair or channel-to-channel

skew (see Note 3)

1.2

ns

t

DVI output clock jitter max (see Note 4)

f

165 MHz

0°C to 70°C

150

ps

DVI output clock jitter, max. (see Note 4)

−55°C to 125°C

190

ps

Data, DE, VSYNC, HSYNC setup time to

IDCK+ falling edge

Single edge

(BSE = 1, DSEL = 0,

DKEN = 0, EDGE = 0)

IDCK = 165 MHz

1.5

ns

Data, DE, VSYNC, HSYNC hold time to

IDCK+ falling edge

Single edge

(BSE = 1, DSEL = 0,

DKEN = 0, EDGE = 0)

IDCK = 165 MHz

1.5

ns

Data, DE, VSYNC, HSYNC setup time to

IDCK+ rising edge

Single edge

(BSEL = 1, DSEL = 0,

DKEN = 0, EDGE = 1)

IDCK = 165 MHz

1.5

ns

Data, DE, VSYNC, HSYNC hold time to

IDCK+ rising edge

Single edge

(BSEL = 1, DSEL = 0,

DKEN = 0, EDGE = 1)

IDCK = 165 MHz

1.5

ns

Data, DE, VSYNC, HSYNC setup time to

IDCK+ falling/rising edge

Dual edge

(BSEL = 0, DSEL = 1,

DKEN = 0)

IDCK = 165 MHz

0.9

ns

Data, DE, VSYNC, HSYNC hold time to

IDCK+ falling/rising edge

Dual edge (BSEL = 0,

DSEL = 1, DKEN = 0)

IDCK = 165 MHz

1

ns

De-skew trim increment

DKEN = 1

IDCK = 165 MHz

350

ps

2. Rise and fall times are measured as the time between 20% and 80% of signal amplitude.

3. Measured differentially at the 50% crossing point using the IDCK+ input clock as a trigger

4. Relative to input clock (IDCK)