TFP410MPAPREP datasheet(7/31 Pages) TI1

7 / 31 page

TFP410-EP

PanelBus

™ DIGITAL TRANSMITTER

SGLS344A − JULY 2006 − REVISED MAY 2011

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

dc specifications

PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Data, DE, VSYNC,

VREF = DVDD

0.7 VDD

VIH

High-level input voltage

Data, DE, VSYNC,

HSYNC, and IDCK+/−

0.5 V ≤ VREF ≤ 0.95 V

VREF + 0.2

VIH

High level input voltage

Other inputs

0.7 VDD

l i

Data, DE, VSYNC,

VREF = DVDD

0.3 VDD

VIL

Low-level input voltage

(CMOS input)

Data, DE, VSYNC,

HSYNC, and IDCK+/−

0.5 V ≤ VREF ≤ 0.95 V

VREF − 0.2

VIL

(CMOS input)

Other inputs

0.3VDD

VOH

High-level digital output voltage (open-drain output) VDD = 3 V, IOH = 20 μA

2.4

VOL

Low-level digital output voltage (open-drain output)

VDD = 3.6 V, IOL = 4 mA

0.4

IIH

High-level input current

VI = 3.6 V

±50

μA

IIL

Low-level input current

VI = 0

±50

μA

DVI single-ended high-level output voltage

AVDD = 3.3 V ± 5%,

RT† = 50 Ω ± 10%,

RTFADJ = 510 Ω ± 1%

AVDD − 0.01

AVDD + 0.01

DVI single-ended low-level output voltage

AVDD = 3.3 V ± 5%,

RT† = 50 Ω ± 10%,

RTFADJ = 510 Ω ± 1%

AVDD − 0.6

AVDD − 0.4

VSWING

DVI single-ended output swing voltage

AVDD = 3.3 V ± 5%,

RT† = 50 Ω ± 10%,

RTFADJ = 510 Ω ± 1%

400

600

mVP-P

VOFF

DVI single-ended standby/off output voltage

AVDD = 3.3 V ± 5%,

RT† = 50 Ω ± 10%,

RTFADJ = 510 Ω ± 1%

AVDD − 0.01

AVDD + 0.01

IPD

Power-down current (see Note 1)

200

500

μA

IIDD

Normal power-supply current

Worst-case pattern‡

200

250

† RT is the single-ended termination resistance at the receiver end of the DVI link.

‡ Black and white checkerboard pattern, each checker is one pixel wide.

NOTE 1: Assumes all inputs to the transmitter are not toggling.

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