TFP410-EP

PanelBus

™ DIGITAL TRANSMITTER

SGLS344A − JULY 2006 − REVISED MAY 2011

3

POST OFFICE BOX 655303

functional block diagram

12/24 Bit

I/F

Data

Format

Universal Input

TMDS Transmitter

Serializer

Serializer

Serializer

Control

For DDC

1.8-V Regulators

With Bypass

Capacitors

PLL

TX2±

TX1±

TX0±

TXC±

TFADJ

IDCK±

DATA[23:0]

DE

VSYNC

HSYNC

EDGE/HTPLG

MSEN

PD

ISEL/RST

BSEL/SCL

DSEL/SDA

Encoder

Encoder

Encoder

CTL/A/DK[3:1]

DKEN

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

Input

A3/DK3

CTL2/A2/DK2

CTL1/A1/DK1

6

7

8

I

The operation of these three multifunction inputs depends on the settings of the ISEL (pin 13) and

DKEN (pin 35) inputs. All three inputs support 3.3-V CMOS signal levels and contain weak pulldown

resistors so that, if left unconnected, they default to all low.

become the control inputs, CTL[2:1], which can be used to send additional information across the DVI

link during the blanking interval (DE = low). Pin 6 is not used.

inputs become the deskew inputs DK[3:1], used to adjust the setup and hold times of the pixel data

inputs DATA[23:0], relative to the clock input IDCK±.

address, A[3:1].

DATA[23:12]

36−47

I

Upper 12 bits of the 24-bit pixel bus

In 24-bit, single-edge input mode (BSEL = high), this bus inputs the top half of the 24-bit pixel bus.

In 12-bit, dual-edge input mode (BSEL = low), these bits are not used to input pixel data. In this mode,

section).

DATA[11:0]

50−55,

58−63

I

Lower 12 bits of the 24-bit pixel bus/12-bit pixel bus input

In 24-bit, single-edge input mode (BSEL = high), this bus inputs the bottom half of the 24-bit pixel bus.

In 12-bit, dual-edge input mode (BSEL = low), this bus inputs one-half a pixel (12 bits) at every latch

edge (both rising and falling) of the clock.