HT45F43 datasheet(34/152 Pages) HOLTEK

34 / 152 page

Write Protection

Protection against inadvertent write operation is provided in several ways. After the device is

powered-on the Write Enable bit in the control register will be cleared preventing any write operations.

Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data Memory Bank 0

will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of

protection against spurious write operations. During normal program operation, ensuring that the

Write Enable bit in the control register is cleared will safeguard against incorrect write operations.

EEPROM Interrupt

The EEPROM write or read interrupt is generated when an EEPROM write or read cycle has ended.

The EEPROM interrupt must first be enabled by setting the EE2I bit in the relevant interrupt register.

However as the EEPROM is contained within a Multi-function Interrupt, the associated

multi-function interrupt enable bit must also be set. When an EEPROM write cycle ends, the E2F

request flag and its associated multi-function interrupt request flag will both be set. If the global,

EEPROM and Multi-function interrupts are enabled and the stack is not full, a jump to the associated

Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function

interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the

application program. More details can be obtained in the Interrupt section.

Programming Considerations

Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced

by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank

Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM

control register exist. Although certainly not necessary, consideration might be given in the application

program to the checking of the validity of new write data by a simple read back process. The WR bit in

the EEC register should be set immediately after the WREN bit is set, otherwise the EEPROM write

cycle will not be executed.

Programming Examples

· Reading data from the EEPROM

- polling method

MOV

A, EEPROM_ADRES

; user defined address

MOV

EEA, A

MOV

A, 040H

; setup memory pointer MP1

MOV

MP1, A

; MP1 points to EEC register

MOV

A, 01H

; setup Bank Pointer

MOV

BP, A

SET

IAR1.1

; set RDEN bit, enable read operations

SET

IAR1.0

; start Read Cycle - set RD bit

BACK:

IAR1.0

; check for read cycle end

JMP

BACK

CLR

IAR1

; disable EEPROM read/write

CLR

MOV

A, EED

; move read data to register

MOV

READ_DATA, A

· Writing Data to the EEPROM

- polling method

MOV

A, EEPROM_ADRES

; user defined address

MOV

EEA, A

MOV

A, EEPROM_DATA

; user defined data

MOV

EED, A

MOV

A, 040H

; setup memory pointer MP1

MOV

MP1, A

; MP1 points to EEC register

MOV

A, 01H

; setup Bank Pointer

MOV

BP, A

SET

IAR1.3

; set WREN bit, enable write operations

SET

IAR1.2

; start Write Cycle - set WR bit

BACK:

IAR1.2

; check for write cycle end

JMP

BACK

CLR

IAR1

; disable EEPROM read/write

CLR

Rev. 1.20

September 15, 2011

HT45F23/HT45F43

8-Bit Flash MCU with Op Amps & Comparators

HT45F43 датащи(PDF) 34 Page - Holtek Semiconductor Inc

HT45F43 датащи(HTML) 34 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL