HT45F43 datasheet(92/152 Pages) HOLTEK

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2C Bus Communication

Communication on the I

2C bus requires four separate steps, a START signal, a slave device address

transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I

bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the

bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the

address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1

2C interrupt will be generated. After entering the interrupt service routine,

the slave device must first check the condition of the HAAS bit to determine whether the interrupt

source originates from an address match or from the completion of an 8-bit data transfer. During a data

transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th

bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave

device to determine whether to go into transmit or receive mode. Before any transfer of data to or from

the I

2C bus, the microcontroller must initialise the bus, the following are steps to achieve this:

Step 1

Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to

²1² to enable the I2C bus.

Step 2

Write the slave address of the device to the I

2C bus address register SIMA.

Step 3

Set the ESIM and SIM Muti-Function interrupt enable bit of the interrupt control register to enable the

SIM interrupt and Multi-function interrupt.

2C Bus Start Signal

The START signal can only be generated by the master device connected to the I

2C bus and not by the

slave device. This START signal will be detected by all devices connected to the I

2C bus. When

detected, this indicates that the I

2C bus is busy and therefore the HBB bit will be set. A START

condition occurs when a high to low transition on the SDA line takes place when the SCL line remains

high.

Rev. 1.20

September 15, 2011

HT45F23/HT45F43

8-Bit Flash MCU with Op Amps & Comparators

S t a r t

W r i t e S l a v e

A d d r e s s t o S I M A

S E T S I M [ 2 : 0 ] = 1 1 0

S E T S I M E N

I 2 C B u s

I n t e r r u p t = ?

Y e s

N o

S E T E S I M a n d M F n E

W a i t f o r I n t e r r u p t

G o t o M a i n P r o g r a m

C L R E S I M

P o l l S I M F t o d e c i d e

w h e n t o g o t o I 2 C B u s I S R

G o t o M a i n P r o g r a m

2C Bus Initialisation Flow Chart

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