HT45F43 datasheet(65/152 Pages) HOLTEK

65 / 152 page

Timer Control Register, can be set high to enable the Timer/Event Counter, however it will not

actually start counting until an active edge is received on the external timer pin.

If the Active Edge Select bit T0E or T1E, which is bit 3 of the Timer Control Register, is low, once a

high to low transition has been received on the external timer pin, TMR0 or TMR1, the Timer/Event

Counter will start counting until the external timer pin returns to its original high level. At this point the

enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. If the

Active Edge Select bit is high, the Timer/Event Counter will begin counting once a low to high

transition has been received on the external timer pin and stop counting when the external timer pin

returns to its original low level. As before, the enable bit will be automatically reset to zero and the

Timer/Event Counter will stop counting. It is important to note that in the Pulse Width Measurement

Mode, the enable bit is automatically reset to zero when the external control signal on the external

timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to

zero under program control.

The residual value in the Timer/Event Counter, which can now be read by the program, therefore

represents the length of the pulse received on the external timer pin. As the enable bit has now been

reset, any further transitions on the external timer pin will be ignored. Not until the enable bit is again

set high by the program can the timer begin further pulse width measurements. In this way, single shot

pulse measurements can be easily Made.

It should be noted that in this mode the Timer/Event Counter is controlled by logical transitions on the

external timer pin and not by the logic level. When the Timer/Event Counter is full and overflows, an

interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the

preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event

Counter Interrupt Enable bit in the Interrupt Control Register, INTC0, is reset to zero.

As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as a

pulse width measurement pin, two things have to happen. The first is to ensure that the Operating

Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Pulse Width

Measurement Mode, the second is to ensure that the port control register configures the pin as an input.

Programmable Frequency Divider

- PFD

The Programmable Frequency Divider provides a means of producing a variable frequency output

suitable for applications requiring a precise frequency generator.

The PFD output is pin-shared with the I/O pin PA5. The PFD function is enabled via PFDEN bit in

MISC register, however, if not enabled, the pin can operate as a normal I/O pin.

The clock source for the PFD circuit can originate from either the timer 0 or timer 1 overflow signal

selected via PFDSELbit in MISC register. The output frequency is controlled by loading the required

values into the timer registers and prescaler registers to give the required division ratio. The timer will

begin to count-up from this preload register value until full, at which point an overflow signal is

generated, causing the PFD output to change state. The timer will then be automatically reloaded with

the preload register value and continue counting-up.

HT45F23/HT45F43

8-Bit Flash MCU with Op Amps & Comparators

Rev. 1.20

September 15, 2011

+ 1

+ 2

+ 3

+ 4

T i m e r

E x t e r n a l T C n

P i n I n p u t

T n O N - w i t h T n E = 0

P r e s c a l e r O u t p u t

I n c r e m e n t

T i m e r C o u n t e r

P r e s c a l e r O u t p u t i s s a m p l e d a t e v e r y f a l l i n g e d g e o f T 1 .

Pulse Width Capture Mode Timing Chart (TnE=0)

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