| поискавой системы для электроныых деталей |
|
ICS1532 датащи(PDF) 15 Page - Integrated Device Technology |
|
|
|||||||||||||||||||||||||||||
ICS1532 датащи(HTML) 15 Page - Integrated Device Technology |
|
15 / 36 page ![]() 110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR MDS 1532 G 15 Revision 060804 www.idt.com ICS1532 28h MCLK-SS0 R/W. D-MK. 7-0 MCLK_SS0 Select MCLK spread-spectrum counter LSB’s bits 7-0 See Reg29 - Controls amount of frequency spread Allowed Values = (288 *N / M) + 8 0 29h MCLK-SS1 R/W. D-MK. 7-4 Reserved Reserved 1010 3-0 MCLK_SS1 Select MCLK spread-spectrum counter MSBs bits 11-8 See Reg28 0 2Ah MCLK-SSOE R/W. D-MK. 7-6 MCLK_SS Select MCLK spread-spectrum gain 0 – 00 = The gain is 1 – 01 = The gain is 2 – 10 = The gain is 4 – 11 = The gain is 8 5 Reserved Reserved 0 4-2 MCLK_PFD Select MCLK Phase/Frequency Detector gain – 000 = Gain is 1 – 001 = Gain is 2 – 010 = Gain is 4 – 011 = Gain is 8 – 100 = Gain is 16, and so forth... 0 1-0 MCLK_OSD Select value for MCLK Output Scaler Divider – 00 = Divide by 1 – 01 = Divide by 2 – 10 = Divide by 4 – 11 = Divide by 8 0 2Bh MCLK-OE R/W 7-2 Reserved Reserved 010000 1 MCLK_SSENB Enable MCLK spread-spectrum (1 = Enabled) 0 0 MCLK_OE Enable MCLK output (1 = Enabled) 0 2Ch OUTPUT MUX R/W 7 High_Drive# Disable high drive for ADC pixel data output pins 0 6 OE_OSC Enable OSCOUT output pin (1 = Enabled) 1 5-4 OSC_Sel Select OSCOUT Output – 00 = OSCOUT source is OSC. – 01 = OSCOUT source is OSCDIVIDER (Reg7) – 10 = OSCOUT source is OSC/2. – 11 = Reserved 0 3 Reserved Reserved 0 2 REFSEL Select REF status 0 1-0 LCKSEL# Select active low output for STATUS (pin 111) Low when selection below is properly locked, else high – 00 = Main Pixel PLL – 01 = MCLK: Memory Clock – 10 = Reserved – 11 = PNLCLK: Panel Clock 1 2Dh PLL Reset Write 7-4 MCLK_Reset Writing 5xh resets MCLK PLL & loads Regs 26h~2Bh N/A 3-0 PNLCLK_Reset Writing xAh resets PNLCLK PLL & loads Regs 20~25h N/A 2Eh-2Fh Reserved N/A 30h ADC CTRL R/W 7 ADC_OE Enable ADC output (1 = Enabled) 0 ?????? 6 ADC_Inv Invert ADCRCLK signal (1=Latch data on rising edge) 0 5 Force_ADC Force ADC Outputs to state of Reg30:3 1 Table 4-2. New Register Set Outline (Continued) Register Index Register Name Register Access Bit # Bit Name Brief Description Reset Value |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |