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ICS1532 датащи(PDF) 18 Page - Integrated Device Technology

номер детали ICS1532
подробное описание детали  110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR
PDF  36 Pages
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производитель  IDT [Integrated Device Technology]
домашняя страница  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS1532 датащи(HTML) 18 Page - Integrated Device Technology

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110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR
ICS1532
MDS 1532 G
18
Revision 060804
www.idt.com
Chapter 5
DPA Operation
Figure 5-1.
DPA Offset (As Determined by Regs 04 and 05)
Table 5-1.
DPA Control
Reg 05:1-0
1. Number of Delay
Element Units
(Decimal)
2. Reg 04:5-0
Max. Value
(Hex)
3. Pixel Clock Range
(MHz)
Bit 1
Bit 0
0
0
16
0F
55
110
0
1
32
1F
27
110
1
0
Reserved
Reserved
1
1
64
3F
14
64
HSYNC
CLK Offset when
DPA_OS [5-0] = 0
.
.
.
.
.
.
One unit of
DPA Delay
tLow
One clock period
tHigh
CLK Offset when
DPA_OS [5-0] = 1
CLK Offset when
DPA_OS [5-0] = 2
CLK Offset when
DPA_OS [5-0] = Max
tHigh
tHigh
tHigh
Fixed delay
≈ 2.5 ns
1 unit of DPA delay
2 units of DPA delay
Maximum units of DPA delay



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