ICS1532 datasheet(14/36 Pages) IDT

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110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR

ICS1532

MDS 1532 G

Revision 060804

www.idt.com

3-0 Chip Minor Rev

Value increments with minor chip revision.

12h

Rd_Reg

Read

7-4 Reserved

Reserved

N/A

PLL_Lock

Pixel PLL lock status - 1 = Locked, 0 = Unlocked

N/A

MCLK_Lock

Memory MCLK lock status - 1 = Locked, 0 = Unlocked

N/A

PCLK_Lock

Panel PLL lock status - 1 = Locked, 0 = Unlocked

N/A

Reserved

N/A

13h-1Fh Reserved

N/A

20h

PNLCLK-M

R/W. D-PK.

7-0 PNLCLK_M

Select value for PNLCLK M Reference Divider

21h

PNLCLK-N

R/W. D-PK.

7-0 PNLCLK_N

Select value for PNLCLK N Feedback Divider

FPNLCLK = (OSC x (N + 8) / (M+2)

22h

PNLCLK-SS0

R/W. D-PK.

7-0 PNLCLK_SS0

Value for PNLCLK spread-spectrum counter LSB’s bits

7-0 - Controls amount of frequency spread

Allowed Values = (288 *N / M) + 8

23h

PNLCLK-SS1

R/W. D-PK.

7-4 Reserved

Reserved

3-0 PNLCLK_SS1

Value for PNLCLK spread-spectrum counter MSBs bits

11-8 See Reg22

24h

PNLCLK-SSOE R/W. D-PK.

7-6 PNLCLK_SS

Select PNLCLK spread-spectrum gain

– 0 = The gain is 1

– 1 = The gain is 2

– 2 = The gain is 4

– 3 = The gain is 8

Reserved

4-2 PNLCLK_PFD

PNLCLK Phase/Frequency Detector gain

– 000 = Gain is 1

– 001 = Gain is 2

– 010= Gain is 4

– 011 = Gain is 8, and so forth...

– 111 = Gain is 128

1-0 PNLCLK_OSD

PNLCLK Output Scaler Divider

– 00 = Divide by 1

– 01 = Divide by 2

– 10= Divide by 4

– 11 = Divide by 8

25h

PNLCLK-OE

R/W

7-3 Reserved

Reserved

11100

CLK_SEL

Select input for PNLCLK PLL

– 0 = PNLCLK PLL input is from the crystal input

– 1 = Input is from ADC_CLK, divided by 16

PNLCLK_SSENB Enable PNLCLK spread-spectrum

PNLCLK_OE

Enable PNLCLK output

26h

MCLK-M

R/W. D-MK.

7-0 MCLK_M

Value for MCLK M Feedback Divider

27h

MCLK-N

R/W. D-MK.

7-0 MCLK_N

Value for MCLK N (Numerator) Feedback Divider

FMCLK = (OSC x (N + 8)) / (M+2)

Table 4-2.

New Register Set Outline (Continued)

Index

Access

Bit #

Bit Name

Brief Description

Reset

Value

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