MDS 1532 G

29

Revision 060804

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ICS1532

Chapter 12

Timing Diagrams

12.1

AC Timing Diagrams

12.1.1

Phase-Locked-Loop Timing for Digital Setup and Hold

The input HSYNC signal is used to generate the REF output signal. In the Phase/Frequency Detector, the

REF signal is compared with ADCSYNC (which provides the recovered HSYNC signal). Table 12-1 gives

the timing for these signals, and Figure 12-1 shows timing characteristics.

Figure 12-1.

Timing for Phase-Locked Loop

Table 12-1.

Phase-Locked-Loop Timing

Time

Period

Timing Description

Min

Typ

Max

Units

t1

Input HSYNC Rise Time to

REF Rise Time

TBD

7

TBD

ns

Tp

ADCRCLK Period

ns

Td

ADCRCLK Duty Cycle

45-55

50-50

55-45

%

t2

ADCSYNC Active Time

4 x Tp

ns

Tp

Input HSYNC Frequency

(Reg 03 and 02) + 8

=

Tp

t1

HSYNC

CLK

ADCSYNC

t2

Td

REF