MDS 1532 G

11

Revision 060804

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ICS1532

Chapter 4

Register Set

The tables in this chapter detail the functionality of the ICS1532 Register Set bits. The tables include the

register locations, the bit positions, names, and definitions, along with their read/write access, reset values,

and any special functions or capabilities.

4.1

Reserved Bits

The ICS1532 has a number of reserved bits throughout the Register Set. These bits provide enhanced test

functions (intended for use only by ICS manufacturing) and calibration functions (intended for use in

production environments).

Important: The customer must not change the value of reserved bits. If the customer changes the default

values of these reserved bits, normal operation of the ICS1532 can be affected.

4.2

Register Set Conventions

Register Set conventions include the following:

but is given to explain the origin of the bit’s name.

4.3

Register Set Abbreviations and Acronyms

Table 4-1 lists and defines abbreviations and acronyms used specifically in this chapter.

Table 4-1.

Register Set Abbreviations and Acronyms

Abbreviation

or Acronym

Definition

D-DPA

Double-Buffered / Dynamic Phase Adjust. Indicates double-buffered registers for

which working registers load during a software Dynamic Phase Adjust reset. (RegA =

xAh )

D-MK

Double-Buffered / Memory Clock. Indicates double-buffered registers for which

working registers load during a software MCLK reset. (Reg2D = 5xh)

D-PK

Double-Buffered / Panel Clock. Indicates double-buffered registers for which working

registers load during a software PNLCLK reset. (Reg2D = xAh)

D-PLL

Double-Buffered / Phase-Locked Loop. Indicates double-buffered registers for which

working registers load during a software pixel PLL reset. (RegA = 5xh)

IN-A

Increment All. Indicates a value that increments with each all-layer revision of the

ICS1532.

Reg

Register

R/W

Read/Write