L3G4200D datasheet(22/42 Pages) STMICROELECTRONICS

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Digital interfaces

L3G4200D

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Doc ID 17116 Rev 3

5.1.1

I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After

this has been transmitted by the master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits and

the eighth bit tells whether the master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first 7 bits after

a start condition with its address. If they match, the device considers itself addressed by the

master.

The slave address (SAD) associated with the L3G4200D is 110100xb. The SDO pin can be

used to modify the least significant bit (LSb) of the device address. If the SDO pin is

connected to the voltage supply, LSb is ‘1’ (address 1101001b). Otherwise, if the SDO pin is

connected to ground, the LSb value is ‘0’ (address 1101000b). This solution permits the

connection and addressing of two different gyroscopes to the same I2C bus.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which

has been addressed is obliged to generate an acknowledge after each byte of data

received.

The I2C embedded in the L3G4200D behaves like a slave device, and the following protocol

must be adhered to. After the START (ST) condition, a slave address is sent. Once a slave

acknowledge (SAK) has been returned, an 8-bit sub-address is transmitted. The 7 LSb

represent the actual register address while the MSB enables address auto-increment. If the

MSb of the SUB field is 1, the SUB (register address) is automatically incremented to allow

multiple data read/write.

The slave address is completed with a read/write bit. If the bit is ‘1’ (read), a REPEATED

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (write)

the master transmits to the slave with the direction unchanged.

Table 13 describes how the

SAD+read/write bit pattern is composed, listing all the possible configurations.

Table 13.

SAD+read/write patterns

Command

SAD[6:1]

SAD[0] = SDO

R/W

SAD+R/W

Read

110100

11010001 (D1h)

Write

110100

11010000 (D0h)

Read

110100

11010011 (D3h)

Write

110100

11010010 (D2h)

Table 14.

Transfer when master is writing one byte to slave

Master

SAD + W

SUB

DATA

Slave

SAK

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