ADP1874ARQZ-0.3-R7 datasheet(24/44 Pages) AD

24 / 44 page

ADP1874/ADP1875

Rev. 0 | Page 24 of 44

VALLEY

TRIP POINTS

LOAD CURRENT

DEMAND

ERROR AMP

OUTPUT

PWM OUTPUT

fSW

CS AMP

OUTPUT

PSEUDO-FIXED FREQUENCY

The ADP1874/ADP1875 employ a constant on-time control

scheme. During steady state operation, the switching frequency

stays relatively constant, or pseudo-fixed. This is due to the one-

shot tON timer that produces a high-side PWM pulse with a fixed

duration, given that external conditions such as input voltage,

output voltage, and load current are also at steady state. During

load transients, the frequency momentarily changes for the

duration of the transient event so that the output comes back

within regulation more quickly than if the frequency were fixed

or if it were to remain unchanged. After the transient event is

complete, the frequency returns to a pseudo-fixed value.

Figure 78. Load Transient Response Operation

To illustrate this feature more clearly, this section describes

one such load transient event—a positive load step—in detail.

During load transient events, the high-side driver output pulse-

width stays relatively consistent from cycle to cycle; however,

the off-time (DRVL on-time) dynamically adjusts according to

the instantaneous changes in the external conditions mentioned.

POWER GOOD MONITORING

The ADP1874/ADP1875 power good circuitry monitors the

output voltage via the FB pin. The PGOOD pin is an open-drain

output that can be pulled up by an external resistor to a voltage

rail that does not necessarily have to be VREG. When the internal

NMOS switch is in high impedance (off state), this means that

the PGOOD pin is logic high, and the output voltage via the FB

pin is within the specified regulation window. When the internal

switch is turned on, PGOOD is internally pulled low when the

output voltage via the FB pin is outside this regulation window.

When a positive load step occurs, the error amplifier (out of phase

with the output, VOUT) produces new voltage information at its

output (COMP). In addition, the current-sense amplifier senses

new inductor current information during this positive load

transient event. The error amplifier’s output voltage reaction is

compared with the new inductor current information that sets

the start of the next switching cycle. Because current information

is produced from valley current sensing, it is sensed at the down

ramp of the inductor current, whereas the voltage loop information

is sensed through the counter action upswing of the error

amplifier’s output (COMP).

The power good window is defined with a typical upper

specification of +90 mV and a lower specification of −70 mV

below the FB voltage of 600 mV. When an overvoltage event occurs

at the output, there is a typical propagation delay of 12 μs prior

to the PGOOD pin deassertion (logic low). When the output

voltage re-enters the regulation window, there is a propagation

delay of 12 μs prior to PGOOD reasserting back to a logic high

state. When the output is outside the regulation window, the

PGOOD open drain switch is capable of sinking 1mA of current

and provides 140 mV of drop across this switch. The user is free

to tie the external pull-up resistor (RRES) to any voltage rail up to

20 V. The following equation provides the proper external pull-up

resistor value:

The result is a convergence of these two signals (see Figure 78),

which allows an instantaneous increase in switching frequency

during the positive load transient event. In summary, a positive

load step causes VOUT to transient down, which causes COMP to

transient up and, therefore, shortens the off time. This resulting

increase in frequency during a positive load transient helps to

quickly bring VOUT back up in value and within the regulation

window.

140

−

= EXT

PGD

Similarly, a negative load step causes the off time to lengthen in

response to VOUT rising. This effectively increases the inductor

demagnetizing phase, helping to bring VOUT within regulation.

In this case, the switching frequency decreases, or experiences a

foldback, to help facilitate output voltage recovery.

where:

RPGD is the PGOOD external resistor.

VEXT is a user-chosen voltage rail.

530mV

690mV

600mV

PGOOD

1mA

–

140mV

VEXT

RPGD

Because the ADP1874/ADP1875 have the ability to respond rapidly

to sudden changes in load demand, the recovery period in which

the output voltage settles back to its original steady state operating

point is much quicker than it would be for a fixed-frequency

equivalent. Therefore, using a pseudo-fixed frequency results in

significantly better load-transient performance compared to

using a fixed frequency.

Figure 79. Power Good, Output Voltage Monitoring Circuit

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