ADP1874ARQZ-0.3-R7 datasheet(19/44 Pages) AD

19 / 44 page

ADP1874/ADP1875

Rev. 0 | Page 19 of 44

THEORY OF OPERATION

The ADP1874/ADP1875 are versatile current mode, synchronous

step-down controllers that provide superior transient response,

optimal stability, and current limit protection by using a constant

on-time, pseudo-fixed frequency with a programmable current-

sense gain, current-control scheme. In addition, these devices offer

optimum performance at low duty cycles by using a valley, current

mode control architecture. This allows the ADP1874/ADP1875

to drive all N-channel power stages to regulate output voltages

to as low as 0.6 V.

STARTUP

The ADP1874/ADP1875 have an internal regulator (VREG) for

biasing and supplying power for the integrated MOSFET drivers.

A bypass capacitor should be located directly across the VREG

(Pin 7) and PGND (Pin 13) pins. Included in the power-up

sequence is the biasing of the current-sense amplifier, the current-

sense gain circuit (see the Programming Resistor (RES) Detect

Circuit section), the soft start circuit, and the error amplifier.

The current-sense blocks provide valley current information

(see the Programming Resistor (RES) Detect Circuit section)

and are a variable of the compensation equation for loop stability

(see the Compensation Network section). The valley current

information is extracted by forcing a voltage across the RES and

PGND pins, which generates a current depending on the resistor

value across RES and PGND. The current through the resistor is

used to set the current-sense amplifier gain. This process takes

approximately 800 μs, after which the drive signal pulses appear

at the DRVL and DRVH pins synchronously, and the output

voltage begins to rise in a controlled manner through the soft

start sequence.

The rise time of the output voltage is determined by the soft

start and error amplifier blocks (see the Soft Start section). At

the beginning of a soft start, the error amplifier charges the

external compensation capacitor, causing the COMP pin to

begin to rise (see Figure 66). Tying the VREG pin to the EN pin

via a pull-up resistor causes the voltage at this pin to rise above the

enable threshold of 630 mV to enable the ADP1874/ADP1875.

SOFT START

The ADP1874 employs externally programmable, soft start

circuitry that charges up a capacitor tied to the SS pin to GND.

This prevents input in-rush current through the external MOSFET

from the input supply (VIN). The output tracks the ramping voltage

by producing PWM output pulses to the upper-side MOSFET.

The purpose is to limit the in-rush current from the high

voltage input supply (VIN) to the output (VOUT).

PRECISION ENABLE CIRCUITRY

The ADP1874/ADP1875 have precision enable circuitry. The

precision enable threshold is 630 mV with 30 mV of hysteresis

(see Figure 65). Connecting the EN pin to GND disables the

ADP1874/ADP1875, reducing the supply current of the device

to approximately 140 μA.

PRECISION

ENABLE COMP.

TO ENABLE

ALL BLOCKS

630mV

VREG

10kΩ

Figure 65. Connecting EN Pin to VREG via a Pull-Up Resistor to Enable the

ADP1874/ADP1875

COMP

2.4V

1.0V

500mV

MAXIMUM CURRENT (UPPER CLAMP)

ZERO CURRENT

USABLE RANGE ONLY AFTER SOFT START

PERIOD IF CONTUNUOUS CONDUCTION

MODE OF OPERATION IS SELECTED.

LOWER CLAMP

Figure 66. COMP Voltage Range

UNDERVOLTAGE LOCKOUT

The undervoltage lockout (UVLO) feature prevents the part from

operating both the upper- and lower-side MOSFETs at extremely

low or undefined input voltage (VIN) ranges. Operation at an

undefined bias voltage may result in the incorrect propagation

of signals to the high-side power switches. This, in turn, results

in invalid output behavior that can cause damage to the output

devices, ultimately destroying the device tied at the output. The

UVLO level is set at 2.65 V (nominal).

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