ADP1874ARQZ-0.3-R7 datasheet(29/44 Pages) AD

29 / 44 page

ADP1874/ADP1875

Rev. 0 | Page 29 of 44

EFFICIENCY CONSIDERATION

One of the important criteria to consider in constructing a dc-to-dc

converter is efficiency. By definition, efficiency is the ratio of the

output power to the input power. For high power applications at

load currents up to 20 A, the following are important MOSFET

parameters that aid in the selection process:

•

VGS (TH) is the MOSFET voltage applied between the gate

and the source that starts channel conduction.

•

RDS (ON) is the MOSFET on resistance during channel

conduction.

•

QG is the total gate charge.

•

CN1 is the input capacitance of the upper-side switch.

•

CN2 is the input capacitance of the lower-side switch.

The following are the losses experienced through the external

component during normal switching operation:

•

Channel conduction loss (both the MOSFETs)

•

MOSFET driver loss

•

MOSFET switching loss

•

Body diode conduction loss (lower-side MOSFET)

•

Inductor loss (copper and core loss)

Channel Conduction Loss

During normal operation, the bulk of the loss in efficiency is due

to the power dissipated through MOSFET channel conduction.

Power loss through the upper-side MOSFET is directly pro-

portional to the duty-cycle (D) for each switching period, and

the power loss through the lower-side MOSFET is directly

proportional to 1 − D for each switching period. The selection

of MOSFETs is governed by the maximum dc load current that

the converter is expected to deliver. In particular, the selection

of the lower-side MOSFET is dictated by the maximum load

current because a typical high current application employs duty

cycles of less than 50%. Therefore, the lower-side MOSFET is

in the on state for most of the switching period.

()

[

] 2

LOAD

N2(ON)

N1(ON)

N1,N2(CL)

−

MOSFET Driver Loss

Other dissipative elements are the MOSFET drivers. The con-

tributing factors are the dc current flowing through a driver

during operation and the QGATE parameter of the external MOSFETs.

(

)

[

]

()

[]

BIAS

REG

lowerFET

BIAS

upperFET

LOSS

VREG

)

(

where:

CupperFET is the input gate capacitance of the upper-side MOSFET.

ClowerFET is the input gate capacitance of the lower-side MOSFET.

IBIAS is the dc current flowing into the upper- and lower-side drivers.

VDR is the driver bias voltage (that is, the low input voltage

(VREG) minus the rectifier drop (see Figure 87)

VREG is the bias voltage.

800

720

640

560

480

400

320

240

160

300

1000

900

800

700

600

500

400

SWITCHING FREQUENCY (kHz)

+125°C

+25°C

–40°C

VREG = 2.7V

VREG = 3.6V

VREG = 5.5V

Figure 87. Internal Rectifier Voltage Drop vs. Switching Frequency

Switching Loss

The SW node transitions due to the switching activities of the

upper- and lower-side MOSFETs. This causes removal and

replenishing of charge to and from the gate oxide layer of the

MOSFET, as well as to and from the parasitic capacitance

associated with the gate oxide edge overlap and the drain and

source terminals. The current that enters and exits these charge

paths presents additional loss during these transition times.

This can be approximately quantified by using the following

equation, which represents the time in which charge enters and

exits these capacitive regions:

tSW-TRANS = RGATE × CTOTAL

where:

CTOTAL is the CGD + CGS of the external MOSFET.

RGATE is the gate input resistance of the external MOSFET.

The ratio of this time constant to the period of one switching cycle

is the multiplying factor to be used in the following expression:

)

(

LOAD

TRANS

LOSS

PSW(LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2

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