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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC5675K датащи(PDF) 19 Page - Freescale Semiconductor, Inc |
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MPC5675K датащи(HTML) 19 Page - Freescale Semiconductor, Inc |
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19 / 140 page  Package pinouts and signal descriptions MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice Freescale Semiconductor 19 2 Package pinouts and signal descriptions 2.1 Package pinouts Figure 2 shows the MPC5675K in the 257 MAPBGA package. Figure 3 through Figure 6 show the MPC5675K in the 473 MAPBGA package. Figure 2. MPC5675K 257 MAPBGA pinout (top view) 12 3456 789 10 11 12 13 14 15 16 17 A VSS_ HV_IO VSS_ HV_IO VDD_ HV_IO nexus MDO[5] nexus MDO[7] nexus MDO[9] flexray CB_TX flexray CA_TR_ EN VDD_ HV_IO fec RXD[2] fec RX_ CLK fec RXD[0] fec MDIO fec TX_EN fec TXD[3] VSS_ HV_IO VSS_ HV_IO A B VSS_ HV_IO VSS_ HV_IO mc_cgl clk_out can1 TXD nexus MDO [14] dspi2 CS1 flexray CB_TR_ EN flexray CA_TX VSS_ HV_IO fec RXD[3] fec RX_ER fec RXD[1] fec TX_ER fec TX_ CLK can0 TXD VDD_ HV_IO VSS_ HV_IO B C VDD_ HV_IO nexus MDO [15] VSS_ HV_IO FCCU_ F[1] flexray CB_RX etimer0 ETC[0] etimer0 ETC[1] etimer0 ETC[2] etimer0 ETC[3] JCOMP fec CRS fec TXD[0] fec COL can0 RXD VSS_ HV_PDI pdi DATA [5] pdi CLOCK C D nexus MDO [2] nexus MDO [3] can1 RXD dspi0 SOUT RESERV ED etimer0 ETC[5] etimer0 ETC[4] VDD_ HV_FLA VSS_ HV_FLA fec TXD[2] fec TXD[1] fec RX_DV fec MDC VDD_ HV_PDI VSS_ HV_IO pdi DATA [0] pdi DATA [1] D E nexus MDO [0] nexus MDO [1] flexray CA_RX NMI pdi LINE_V pdi DATA [2] pdi DATA [3] pdi DATA [4] E F nexus MDO[6] nexus MDO [11] dspi1 SOUT dspi1 SIN VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR mc_cgl clk_out pdi DATA [6] pdi DATA [7] pdi DATA [8] F G nexus MDO [4] VDD_ HV_IO dspi0 SCK dspi1 SCK VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR pdi DATA [9] pdi DATA [10] pdi DATA [11] pdi FRAME_ V G H nexus MDO [10] VSS_ HV_IO dspi0 CS0 dspi1 CS0 VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR pdi DATA [12] pdi DATA [13] VDD_ HV_ PDI flexpwm 0 X[0] H J nexus MCKO nexus MDO[8] dspi2 CS0 dspi2 CS2 VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR pdi DATA [14] pdi DATA [15] VSS_ HV_ PDI flexpwm 0 X[1] J K nexus MSEO_ B[0] nexus MSEO_ B[1] nexus RDY_B dspi0 SIN VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR flexpwm 0 X[2] flexpwm 0 X[3] flexpwm 0 A[1] flexpwm 0 B[0] K L nexus EVTO_B nexus EVTI_B dspi2 SCK nexus MDO [13] VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR VDD_HV _DRAM_ VREF TCK flexpwm 0 B[1] TDO L M VDD_ HV_ OSC VDD_ HV_IO dspi1 CS2 nexus MDO [12] VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR flexpwm 0 B[2] TDI TMS flexpwm 1 A[1] M N XTALIN VSS_ HV_IO dspi0 CS3 VSS_ LV_PLL flexpwm 0 B[3] flexpwm 0 A[2] flexpwm 1 A[0] flexpwm 1 B[0] N P VSS_ HV_ OSC RESET dspi0 CS2 VDD_ LV_PLL etimer1 ETC[1] etimer1 ETC[2] adc0 AN[0] etimer1 ETC[3] VSS_ HV_IO VDD_ HV_IO adc0_ adc1 AN[14] etimer1 ETC[4] etimer1 ETC[5] VDD_ HV_IO flexpwm 0 A[3] flexpwm 0 A[0] flexpwm 1 B[1] P R XTAL OUT FCCU_ F[0] VSS_HV _IO dspi1 CS3 adc2 AN[0] adc2 AN[3] VDD_ HV_ ADR_13 adc2_ adc3 AN[14] VDD_ HV_ ADR_02 adc0 AN[2] adc0_ adc1 AN[13] adc1 AN[1] VREG_C TRL lin0 TXD VSS_ HV_IO flexpwm 1 A[2] flexpwm 1 B[2] R T VSS_ HV_IO VDD_ HV_IO dspi2 SOUT adc3 AN[0] adc3 AN[3] adc2 AN[2] VSS_ HV_ ADR_13 adc2_ adc3 AN[13] VSS_ HV_ ADR_02 adc0 AN[1] adc0_ adc1 AN[12] adc1 AN[0] adc1 AN[2] lin0 RXD etimer1 ETC[0] VDD_ HV_IO VSS_ HV_IO T U VSS_ HV_IO VSS_ HV_IO dspi2 SIN adc3 AN[1] adc3 AN[2] adc2 AN[1] adc2_ adc3 AN[11] adc2_ adc3 AN[12] VDD_ HV_ ADV VSS_ HV_ ADV adc0_ adc1 AN[11] VREG_ INT_EN ABLE RESET_ SUP VDD_HV _PMU VSS_ HV_ PMU VSS_ HV_IO VSS_ HV_IO U 12 3456 789 10 11 12 13 14 15 16 17 |
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