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MPC5675K датащи(PDF) 18 Page - Freescale Semiconductor, Inc

номер детали MPC5675K
подробное описание детали  Microcontroller is a 32-bit embedded controller designed for advanced
PDF  140 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5675K датащи(HTML) 18 Page - Freescale Semiconductor, Inc

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MPC5675K Microcontroller Data Sheet, Rev. 4
Preliminary—Subject to Change Without Notice
Overview
Freescale Semiconductor
18
1.4.26
Non-maskable interrupt (NMI)
The non-maskable interrupt with de-glitching filter is available to support high priority core exceptions.
1.4.27
System Status and Configuration Module (SSCM)
The SSCM on the MPC5675K features the following:
System configuration and status
Debug port status and debug port enable
Multiple boot code starting locations out of reset through implementation of search for valid Reset
Configuration Half Word
Sets up the MMU to allow user boot code to execute as either Classic PowerPC Book E code
(default) or as Freescale VLE code out of flash
Supports serial bootloading of either Classic PowerPC Book E code (default) or Freescale VLE code
Detection of user boot code
Automatic switch to serial boot mode if internal flash is blank or invalid
1.4.28
Nexus Development Interface (NDI)
Per IEEE-ISTO 5001-2008
Real-time development support for Power Architecture core through Nexus class 3 (some class 4
support)
Nexus support to snoop system SRAM traffic
Data trace of FlexRay accesses
Read and write access
Configured via the IEEE 1149.1 (JTAG) port
High bandwidth mode for fast message transmission
Reduced bandwidth mode for reduced pin usage
1.4.29
IEEE 1149.1 JTAG controller (JTAGC)
IEEE 1149.1-2001 Test Access Port (TAP) interface
JCOMP input that provides the ability to share the TAP —selectable modes of operation include
JTAGC/debug or normal system operation
5-bit instruction register that supports IEEE 1149.1-2001 defined instructions
5-bit instruction register that supports additional public instructions
Three test data registers:
— Bypass register
— Boundary scan register
— Device identification register
TAP controller state machine that controls the operation of the data registers, instruction register,
and associated circuitry



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