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MPC5675K датащи(PDF) 72 Page - Freescale Semiconductor, Inc

номер детали MPC5675K
подробное описание детали  Microcontroller is a 32-bit embedded controller designed for advanced
PDF  140 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5675K датащи(HTML) 72 Page - Freescale Semiconductor, Inc

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MPC5675K Microcontroller Data Sheet, Rev. 4
Preliminary—Subject to Change Without Notice
Electrical characteristics
Freescale Semiconductor
72
2VSS_HV_PMU
SR Voltage regulator supply ground
—0
0
V
3VDD_HV_IO
SR Input/output supply voltage
—3.0
3.6
V
4VSS_HV_IO
SR Input/output supply ground
—0
0
V
5VDD_HV_FLA
SR Flash supply voltage
—3.0
3.6
V
6VSS_HV_FLA
SR Flash supply ground
—0
0
V
7VDD_HV_OSC
SR Crystal oscillator amplifier supply voltage
—3.0
3.6
V
8VSS_HV_OSC
SR Crystal oscillator amplifier supply ground
—0
0
V
9VDD_HV_PDI
SR PDI interface supply voltage
—
1.62
3.6
V
10
VSS_HV_PDI
SR PDI interface supply ground
—0
0
V
11
VDD_HV_DRAM
SR DRAM interface supply voltage
—
1.62
3.6
V
12
VSS_HV_DRAM
SR DRAM interface supply ground
—0
0
V
13
VDD_HV_ADRx
SR ADCx high reference voltage
—3.0
3.6
V
Alternate input
voltage
4.5
5.5
14
VSS_HV_ADRx
SR ADCx low reference voltage
—0
0
V
15
VDD_HV_ADV
SR ADC supply voltage
—3.0
3.6
V
16
VSS_HV_ADV
SR ADC supply ground
—0
0
V
17
VDD_LV_COR
SR Core supply voltage digital logic2
External VREG
mode
1.14
1.32
V
17a
CC
Internal VREG
Mode
1.14
1.32
V
18
VSS_LV_COR
SR Core supply voltage ground digital logic
—0
0
V
19
VDD_LV_PLL
SR PLL supply voltage2
External VREG
mode
1.14
1.32
V
19a
CC
Internal VREG
Mode
1.14
1.32
V
20
VSS_LV_PLL
SR PLL reference voltage
—0
0
V
21
TA
SR Ambient temperature under bias3
257 MAPBGA
–40
1054
°C
473 MAPBGA
–40
125
°C
22
TJ
SR Junction temperature under bias
257 MAPBGA
–40
150
°C
473 MAPBGA
–40
150
NOTES:
1 These specifications are design targets and are subject to change per device characterization.
2 The jitter specifications for both PLLs holds true only up to 50 mV noise (peak to peak) on V
DD_LV_COR and
VDD_LV_PLL.
3 See Table 1 for available frequency and package options.
4 Preliminary data.
Table 12. Recommended operating conditions1 (continued)
No.
Symbol
Parameter
Conditions
Min
Max
Unit



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