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IXP45X датащи(PDF) 119 Page - Intel Corporation |
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IXP45X датащи(HTML) 119 Page - Intel Corporation |
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119 / 148 page ![]() Intel® IXP45X and Intel® IXP46X Product Line of Network Processors August 2006 Datasheet Document Number: 306261-004US 119 Datasheet—Intel® IXP45X and Intel® IXP46X Product Line of Network Processors 5.6.2.4 MII/SMII Table 55. UTOPIA Level 2 Output Timings Values Symbol Parameter Min. Max. Units Notes Tclk2out Rising edge of clock to signal output. Outputs included in this timing are UTP_OP_SOC, UTP_OP_FCO, UTP_IP_FCO, UTP_OP_DATA[7:0], UTP_IP_ADDR[4:0] and UTP_OP_ADDR[4:0]. 17 ns 1 Tholdout Signal output hold time after the rising edge of the clock. Outputs included in this timing are UTP_OP_SOC, UTP_OP_FCO, UTP_IP_FCO, UTP_OP_DATA[7:0], UTP_IP_ADDR[4:0] and UTP_OP_ADDR[4:0]. 1ns 1 Notes: 1. Timing was designed for a system load between 5pF and 25pF Figure 21. SMII Output Timings Table 56. SMII Output Timings Values Symbol Parameter Min. Max. Units Notes T1 Clock to output delay for SMII_TXD[4:0] and SMII_SYNC with respect to rising edge of SMII_CLK 1.5 5 ns 1 T2 SMII_TXD[4:0] and SMII_SYNC hold time after SMII_CLK. 1.5 ns 1 Notes: 1. Timing was designed for a system load between 5pF and 15pF SMII_CLK SMII_OUTPUTS T 1 T 2 |
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