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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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335 датащи(PDF) 18 Page - Intel Corporation |
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335 датащи(HTML) 18 Page - Intel Corporation |
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18 / 82 page  18 Datasheet Electrical Specifications 2.4.1 Phase Lock Loop (PLL) Power and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Celeron D processor silicon. Since these PLLs are analog, they require low noise power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCC. The AC low-pass requirements, with input at VCC are as follows: • < 0.2 dB gain in pass band • < 0.5 dB attenuation in pass band < 1 Hz • > 34 dB attenuation from 1 MHz to 66 MHz • > 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 2-1. . NOTES: 1. Diagram not to scale. 2. No specification exists for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz. Figure 2-1. Phase Lock Loop (PLL) Filter Requirements 0 dB –28 dB –34 dB 0.2 dB –0.5 dB 1 MHz 66 MHz fcore fpeak 1 Hz DC Passband High Frequency Band Forbidden Zone Forbidden Zone |
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