DSM2180F3 datasheet(4/63 Pages) STMICROELECTRONICS

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DSM2180F3

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SUMMARY DESCRIPTION

These are system memory devices for use with

Digital Signal Processors from the popular Analog

Devices ADSP-218X family. DSM means Digital

signal processor System Memory. A DSM device

brings in-system programmable Flash memory,

programmable logic, and additional I/O to DSP

systems. The result is a simple and flexible two-

chip solution for DSP designs. DSM devices pro-

vide the flexibility of Flash memory and smart

JTAG programming techniques for both manufac-

turing and the field. On-chip integrated memory

decode logic and memory paging logic make it

easy to add large amounts of external Flash mem-

ory to the ADSP-218X family for bootloading upon

power-up and/or overlay memory. The DSP ac-

cesses this Flash memory using either its Byte

DMA (BDMA) interface or as external data overlay

memory (no DMA setup overhead).

Figure 2. PLCC Connections

JTAG In-System Programming (ISP) reduces de-

velopment time, simplifies manufacturing flow,

and lowers the cost of field upgrades. The JTAG

ISP interface eliminates the need for sockets and

pre-programmed memory and logic devices. For

manufacturing, end products may be assembled

with a blank DSM device soldered to the circuit

board and programmed at the end of the manufac-

turing line in 10 to 20 seconds with no involvement

of the DSP. This allows efficient means to test

product and manage inventory by rapidly pro-

gramming test code, then application code as de-

termined by inventory requirements (Just-In Time

inventory). Additionally, JTAG ISP reduces devel-

opment time by turning fast iterations of DSP code

in the lab. Code updates in the field require no dis-

assembly of product. The FlashLINKTM JTAG pro-

gramming cable costs $59 USD and plugs into any

PC or note-book parallel port.

Figure 3. PQFP Connections

In addition to ISP Flash memory, DSM devices

add programmable logic (PLD) and up to 16 con-

figurable I/O pins to the DSP system. The state of

each I/O pin can be driven by DSP software or

PLD logic. PLD and I/O configuration are program-

mable by JTAG ISP, just like the Flash memory.

The PLD consists of more than 3000 gates and

has 16 macro cell registers. Common uses for the

PLD include chip selects for external devices (i.e.

UART), state-machines, simple shifters and coun-

ters, keypad and control panel interfaces, clock di-

viders,

handshake

delay,

muxes,

etc.

This

eliminates the need for small external PLDs and

logic devices. Configuration of PLD, I/O, and Flash

memory mapping are easily entered in a point-

and-click environment using the software develop-

ment tool, PSDsoft ExpressTM. This software is

available at no charge from www.psdst.com.

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

VCC

AD7

AD6

AD5

AD4

PD2

PD1

PD0

PC7

PC6

PC5

PC4

VCC

GND

PC3

PC2

PC1

PC0

AI02857

39 AD15

38 AD14

37 AD13

36 AD12

35 AD11

34 AD10

33 AD9

32 AD8

31 VCC

30 AD7

29 AD6

28 AD5

27 AD4

PD2

PD1

PD0

PC7

PC6

PC5

PC4

VCC

GND

PC3

PC2

PC1

PC0

AI02858

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