DSM2180F3 datasheet(28/63 Pages) STMICROELECTRONICS

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DSM2180F3

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COMPLEX PLD (CPLD)

The CPLD can be used to implement system logic

functions, such as loadable counters and shift reg-

isters, system mailboxes, handshaking protocols,

state machines, and random logic. See application

note AN1171 for details on how to specify logic us-

ing PSDsoft Express.

As shown in Figure 15, the CPLD has the following

blocks:

■ 16 Input Macrocells (IMC)

■ 16 Output Macrocells (OMC)

■ Macrocell Allocator

■ Product Term Allocator

■ AND Array capable of generating up to 130

product terms

■ Two I/O Ports.

Each of the blocks are described in the sections

that follow.

The Input Macrocells (IMC) and Output Macrocells

(OMC) are connected to the device internal data

bus and can be directly accessed by the DSP. This

enables the DSP software to load data into the

Output Macrocells (OMC) or read data from both

the Input and Output Macrocells (IMC and OMC).

This feature allows efficient implementation of sys-

tem logic and eliminates the need to connect the

data bus to the AND Array as required in most

standard PLD macro cell architectures.

Figure 15. Macrocell and I/O Port

Output Macrocell (OMC). Eight of the Output

Macrocells (OMC) are connected to Port B pins

and are named as McellAB0-McellAB7. The other

eight Macrocells are connected to Ports B or C

pins and are named as McellBC0-McellBC7.

OMCs may be used for internal feedback only

(buried registers), or their outputs may be routed

to external Port pins.

The Output Macrocell (OMC) architecture is

shown in Figure 17. As shown in the figure, there

are native product terms available from the AND

Array, and borrowed product terms available (if

unused) from other Output Macrocells (OMC). The

polarity of the product term is controlled by the

XOR gate. The Output Macrocell (OMC) can im-

plement either sequential logic, using the flip-flop

I/O PORTS

CPLD Macrocells

Input Macrocells

LATCHED

ADDRESS OUT

MUX

PDR

DATA

PRODUCT TERM

ALLOCATOR

DIR

REG.

SELECT

INPUT

Product Terms

from other

MacrocellS

POLARITY

SELECT

UP TO 10

PRODUCT TERMS

CLOCK

SELECT

DI LD

D/T

D/T/JK FF

SELECT

PT CLEAR

CLOCK

GLOBAL

CLOCK

PT Output Enable (OE)

Macrocell Feedback

I/O Port Input

PT INPUT LATCH GATE/CLOCK

MCU LOAD

PT PRESET

MCU DATA IN

COMB.

/REG

SELECT

Macrocell

I/O Port

Alloc.

CPLD

OUTPUT

TO OTHER I/O PORTS

DSP ADDRESS / DATA BUS

Macrocell

Out to

MCU

DATA

LOAD

CONTROL

CPLD OUTPUT

I/O Pin

AI04902B

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