DSM2180F3 datasheet(18/63 Pages) STMICROELECTRONICS

18 / 63 page

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DSM2180F3

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DETAILED OPERATION

Figure 5 shows major functional areas of the de-

vice:

■ Flash Memory

■ PLDs (DPLD, CPLD, Page Register)

■ DSP Bus Interface (Address, Data, Control)

■ I/O Ports

■ Runtime Control Registers

■ JTAG ISP Interface

The following describes these functions in more

detail.

Flash Memory

The Flash memory array is divided evenly into

eight equal 16K byte sectors. Each sector is se-

lected by the DPLD can be separately protected

from program and erase cycles. This configuration

is specified by using PSDsoft ExpressTM.

Memory Sector Select Signals. The DPLD gen-

erates the Select signals for all the internal memo-

ry blocks (see Figure 14). Each of the eight sectors

of the Flash memory has a Select signal (FS0-

FS7) which contains up to three product terms.

Having three product terms for each Select signal

allows a given sector to be mapped into multiple

areas of system memory.

Ready/Busy (PC3). This signal can be used to

output the Ready/Busy status of the device. The

output on Ready/Busy (PC3) is a 0 (Busy) when

Flash memory is being written, or when Flash

memory is being erased. The output is a 1 (Ready)

when no Write or Erase cycle is in progress. This

signal may be polled by the DSP or used as a DSP

interrupt to indicate when an erase or program cy-

cle is complete.

Memory Operation. The Flash memory is ac-

cessed through the DSP Address, Data, and Con-

trol Bus Interface. The DSP can access Flash

memory as BDMA mode or as External Data

Memory Overlay. But from the DSM perspective, it

sees either type of access as a series of byte op-

erations (reads and writes). If the DSP accesses

the DSM in BDMA mode, then the DSP BDMA

channel must be initialized and run for each byte

(or block of bytes) read from Flash memory or it

must initialize the DMA channel for each byte writ-

ten to Flash memory. Alternatively, if the DSP ac-

cesses the DSM in External Data Memory Overlay

mode, then the DSP must only ensure the PSD

Page Register and the DSP DMOVLAY register

contains the correct value, then it performs a nor-

mal data read or data write operation without the

burden of initializing the BDMA channel for each

operation (upper byte of 16-bit word is ignored).

DSPs and MCUs cannot write to Flash memory as

it would an SRAM device. Flash memory must first

be “unlocked” with a special sequence of byte

write operations to invoke an internal algorithm,

then a single data byte is written to the Flash mem-

ory array, then programming status is checked by

a byte read operation or by checking the Ready/

Busy pin (PC3). Table 5 lists all of the special in-

struction sequences to program (write) data to the

Flash memory array, erase the array, and check

for different types of status from the array. These

instruction sequences are different combinations

of individual byte write and byte read operations.

Once the Flash memory array is programmed

(written) and then it is in “Read Array” mode, the

DSP will read from Flash memory just as if would

from any 8-bit ROM or SRAM device.

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