DSM2180F3 datasheet(22/63 Pages) STMICROELECTRONICS

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gram or Erase cycle is in progress or has complet-

ed. Figure 10 shows the Data Polling algorithm.

When the DSP issues a Program instruction se-

quence, the embedded algorithm within the device

begins. The DSP then reads the location of the

byte to be programmed in Flash memory to check

status. The Data Polling Flag (DQ7) bit of this lo-

cation becomes the compliment of bit 7 of the orig-

inal data byte to be programmed. The DSP

continues to poll this location, comparing the Data

Polling Flag (DQ7) bit and monitoring the Error

Flag (DQ5) bit. When the Data Polling Flag (DQ7)

bit matches bit7 of the original data, and the Error

Flag (DQ5) bit remains 0, then the embedded al-

gorithm is complete. If the Error Flag (DQ5) bit is

1, the DSP should test the Data Polling Flag (DQ7)

bit again since the Data Polling Flag (DQ7) bit may

have changed simultaneously with the Error Flag

(DQ5) bit (see Figure 10).

The Error Flag (DQ5) bit is set if either an internal

time-out occurred while the embedded algorithm

attempted to program the byte or if the DSP at-

tempted to program a 1 to a bit that was not erased

(not erased is logic 0).

It is suggested (as with all Flash memories) to read

the location again after the embedded program-

ming algorithm has completed, to compare the

byte that was written to the Flash memory with the

byte that was intended to be written.

When using the Data Polling method during an

Erase cycle, Figure 10 still applies. However, the

Data Polling Flag (DQ7) bit is 0 until the Erase cy-

cle is complete. A 1 on the Error Flag (DQ5) bit in-

dicates a time-out condition on the Erase cycle, a

0 indicates no error. The DSP can read any loca-

tion within the sector being erased to get the Data

Polling Flag (DQ7) bit and the Error Flag (DQ5) bit.

PSDsoft Express generates ANSI C code func-

tions which implement these Data Polling algo-

rithms.

Figure 10. Data Polling Flowchart

Data Toggle. Checking the Toggle Flag (DQ6) bit

is a method of determining whether a Program or

Erase cycle is in progress or has completed. Fig-

ure 11 shows the Data Toggle algorithm.

When the DSP issues a Program instruction se-

quence, the embedded algorithm within the device

begins. The DSP then reads the location of the

byte to be programmed in Flash memory to check

status. The Toggle Flag (DQ6) bit of this location

toggles each time the DSP reads this location until

the embedded algorithm is complete. The DSP

continues to read this location, checking the Tog-

gle Flag (DQ6) bit and monitoring the Error Flag

(DQ5) bit. When the Toggle Flag (DQ6) bit stops

toggling (two consecutive reads yield the same

value), and the Error Flag (DQ5) bit remains 0,

then the embedded algorithm is complete. If the

Error Flag (DQ5) bit is 1, the DSP should test the

Toggle Flag (DQ6) bit again, since the Toggle Flag

(DQ6) bit may have changed simultaneously with

the Error Flag (DQ5) bit (see Figure 11).

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

FAIL

PASS

AI01369B

DQ7

DATA

YES

DQ5

= 1

DQ7

DATA

YES

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