PIC18F23K20-ESLASHML datasheet(147/456 Pages) MICROCHIP

147 / 456 page

 2010 Microchip Technology Inc.

DS41303G-page 147

PIC18F2XK20/4XK20

11.3

Compare Mode

In Compare mode, the 16-bit CCPRx register value is

constantly compared against either the TMR1 or TMR3

can be:

• driven high

• driven low

• toggled (high-to-low or low-to-high)

• remain unchanged (that is, reflects the state of the

I/O latch)

The action on the pin is based on the value of the mode

select bits (CCPxM<3:0>). At the same time, the inter-

rupt flag bit, CCPxIF, is set.

11.3.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the appropriate TRIS bit.

11.3.2

TIMER1/TIMER3 MODE SELECTION

Timer1 and/or Timer3 must be running in Timer mode

or Synchronized Counter mode if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation will not work reliably.

11.3.3

SOFTWARE INTERRUPT MODE

When the Generate Software Interrupt mode is chosen

(CCPxM<3:0> = 1010), the corresponding CCPx pin is

not affected. Only the CCPxIF interrupt flag is affected.

11.3.4

SPECIAL EVENT TRIGGER

Both CCP modules are equipped with a Special Event

Trigger. This is an internal hardware signal generated

in Compare mode to trigger actions by other modules.

The Special Event Trigger is enabled by selecting

the

Compare

Special

Event

Trigger

mode

(CCPxM<3:0> = 1011).

For either CCP module, the Special Event Trigger resets

the timer register pair for whichever timer resource is

currently assigned as the module’s time base. This

allows the CCPRx registers to serve as a programmable

period register for either timer.

The Special Event Trigger for CCP2 can also start an

A/D conversion. In order to do this, the A/D converter

must already be enabled.

FIGURE 11-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

Note:

Clearing the CCPxCON register will force

the CCPx compare output latch (depend-

ing on device configuration) to the default

low level. This is not the PORTB or

PORTC I/O data latch.

CCPR1H

CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set CCP1IF

CCP1 pin

TRIS

CCP1CON<3:0>

Output Enable

TMR3H

TMR3L

CCPR2H

CCPR2L

Comparator

T3CCP2

T3CCP1

Set CCP2IF

Compare

(Timer1/Timer3 Reset)

Output

Logic

Special Event Trigger

CCP2 pin

TRIS

CCP2CON<3:0>

Output Enable

(Timer1/Timer3 Reset, A/D Trigger)

Match

Compare

Match

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