PIC18F23K20-ESLASHML datasheet(38/456 Pages) MICROCHIP

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PIC18F2XK20/4XK20

DS41303G-page 38

 2010 Microchip Technology Inc.

2.10

Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external

oscillator start-up and code execution. In applications

that make heavy use of the Sleep mode, Two-Speed

Start-up will remove the external oscillator start-up

time from the time spent awake and can reduce the

overall power consumption of the device.

This mode allows the application to wake-up from

Sleep, perform a few instructions using the HFINTOSC

as the clock source and go back to Sleep without

waiting for the primary oscillator to become stable.

When the Oscillator module is configured for LP, XT or

HS modes, the Oscillator Start-up Timer (OST) is

enabled (see Section 2.4.1 “Oscillator Start-up Timer

(OST)”). The OST will suspend program execution until

1024 oscillations are counted. Two-Speed Start-up

mode minimizes the delay in code execution by

operating from the internal oscillator as the OST is

counting. When the OST count reaches 1024 and the

OSTS bit of the OSCCON register is set, program

execution switches to the external oscillator.

2.10.1

TWO-SPEED START-UP MODE

CONFIGURATION

Two-Speed Start-up mode is enabled when all of the

following settings are configured as noted:

• Two-Speed Start-up mode is enabled by setting

the IESO of the CONFIG1H Configuration register

is set. Fail-Safe mode (FCMEM = 1) also enables

two-speed by default.

• SCS<1:0> (of the OSCCON register) = 00.

• FOSC<2:0> bits of the CONFIG1H Configuration

Two-Speed Start-up mode becomes active after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

If the external clock oscillator is configured to be

anything other than LP, XT or HS mode, then Two-

Speed Start-up is disabled. This is because the

external

clock

oscillator

does

not

require

any

stabilization time after POR or an exit from Sleep.

2.10.2

TWO-SPEED START-UP

SEQUENCE

Wake-up from Power-on Reset or Sleep.

Instructions begin executing by the internal

oscillator at the frequency set in the IRCF<2:0>

bits of the OSCCON register.

OST enabled to count 1024 external clock

cycles.

OST timed out. External clock is ready.

OSTS is set.

Clock switch finishes according to FIGURE 2-7:

“Clock Switch Timing”

2.10.3

CHECKING TWO-SPEED CLOCK

STATUS

Checking the state of the OSTS bit of the OSCCON

from the external clock source, as defined by the

FOSC<2:0> bits in CONFIG1H Configuration register,

or the internal oscillator. OSTS = 0 when the external

oscillator is not ready, which indicates that the system

is running from the internal oscillator.

Note:

Executing a SLEEP instruction will abort

the oscillator start-up time and will cause

the OSTS bit of the OSCCON register to

remain clear.

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