PIC18F23K20-ESLASHML datasheet(34/456 Pages) MICROCHIP

34 / 456 page

PIC18F2XK20/4XK20

DS41303G-page 34

 2010 Microchip Technology Inc.

2.5.3

LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is

a 31 kHz internal clock source.

The output of the LFINTOSC connects to internal

oscillator block frequency selection multiplexer (see

Figure 2-1). Select 31 kHz, via software, using the

IRCF<2:0> bits of the OSCCON register and the

INTSRC

bit

the

OSCTUNE

See

Section 2.5.4 “Frequency Select Bits (IRCF)” for

more information. The LFINTOSC is also the frequency

for the Power-up Timer (PWRT), Watchdog Timer

(WDT) and Fail-Safe Clock Monitor (FSCM).

The LFINTOSC is enabled when any of the following

are enabled:

• IRCF<2:0> bits of the OSCCON register = 000 and

INTSRC bit of the OSCTUNE register = 0

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

2.5.4

FREQUENCY SELECT BITS (IRCF)

The output of the 16 MHz HFINTOSC and 31 kHz

LFINTOSC connects to a postscaler and multiplexer

(see Figure 2-1). The Internal Oscillator Frequency

Select bits IRCF<2:0> of the OSCCON register select

the output frequency of the internal oscillators. One of

eight frequencies can be selected via software:

•16 MHz

•8 MHz

•4 MHz

•2 MHz

• 1 MHz (Default after Reset)

• 500 kHz

• 250 kHz

• 31 kHz (LFINTOSC or HFINTOSC/512)

2.5.5

HFINTOSC FREQUENCY DRIFT

The factory calibrates the internal oscillator block output

(HFINTOSC) for 16 MHz. However, this frequency may

drift as VDD or temperature changes, which can affect the

controller operation in a variety of ways. It is possible to

adjust the HFINTOSC frequency by modifying the value

of the TUN<5:0> bits in the OSCTUNE register. This has

no effect on the LFINTOSC clock source frequency.

Tuning the HFINTOSC source requires knowing when to

make the adjustment, in which direction it should be

made and in some cases, how large a change is

needed. Three possible compensation techniques are

discussed in the following sections, however other tech-

niques may be used.

2.5.5.1

Compensating with the USART

An adjustment may be required when the USART

begins to generate framing errors or receives data with

errors while in Asynchronous mode. Framing errors

indicate that the device clock frequency is too high; to

adjust for this, decrement the value in OSCTUNE to

reduce the clock frequency. On the other hand, errors

in data may suggest that the clock speed is too low; to

compensate, increment OSCTUNE to increase the

clock frequency.

2.5.5.2

Compensating with the Timers

This technique compares device clock speed to some

reference clock. Two timers may be used; one timer is

clocked by the peripheral clock, while the other is

clocked by a fixed reference source, such as the

Timer1 oscillator.

Both timers are cleared, but the timer clocked by the

reference generates interrupts. When an interrupt

occurs, the internally clocked timer is read and both

timers are cleared. If the internally clocked timer value

is greater than expected, then the internal oscillator

block is running too fast. To adjust for this, decrement

the OSCTUNE register.

2.5.5.3

Compensating with the CCP Module

in Capture Mode

A CCP module can use free running Timer1 (or Timer3),

clocked by the internal oscillator block and an external

event with a known period (i.e., AC power frequency).

The time of the first event is captured in the

CCPRxH:CCPRxL registers and is recorded for use later.

When the second event causes a capture, the time of the

first event is subtracted from the time of the second

event. Since the period of the external event is known,

the time difference between events can be calculated.

If the measured time is much greater than the calcu-

lated time, the internal oscillator block is running too

fast; to compensate, decrement the OSCTUNE register.

If the measured time is much less than the calculated

time, the internal oscillator block is running too slow; to

compensate, increment the OSCTUNE register.

Note:

Following any Reset, the IRCF<2:0> bits of

the OSCCON register are set to ‘011’ and

the frequency selection is set to 1 MHz.

The user can modify the IRCF bits to

select a different frequency.

PIC18F23K20-E/ML датащи(PDF) 34 Page - Microchip Technology

PIC18F23K20-E/ML датащи(HTML) 34 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL