PIC18F23K20-ESLASHML datasheet(45/456 Pages) MICROCHIP

45 / 456 page

 2010 Microchip Technology Inc.

DS41303G-page 45

PIC18F2XK20/4XK20

3.2.3

RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are

clocked from the internal oscillator block using one of

the selections from the HFINTOSC multiplexer. In this

mode, the primary oscillator is shut down. RC_RUN

mode provides the best power conservation of all the

Run modes when the LFINTOSC is the main clock

source. It works well for user applications which are not

highly timing sensitive or do not require high-speed

clocks at all times.

If the primary clock source is the internal oscillator

block (either LFINTOSC or HFINTOSC), there are no

distinguishable differences between PRI_RUN and

RC_RUN modes during execution. However, a clock

switch delay will occur during entry to and exit from

RC_RUN mode. Therefore, if the primary clock source

is the internal oscillator block, the use of RC_RUN

mode is not recommended. See 2.9.3 “Clock Switch

Timing” for details about clock switching.

RC_RUN mode is entered by setting the SCS1 bit to

‘1’. The SCS0 bit can be either ‘0’ or ‘1’ but should be

‘0’ to maintain software compatibility with future

devices. When the clock source is switched from the

primary oscillator to the HFINTOSC multiplexer, the pri-

mary oscillator is shut down and the OSTS bit is

cleared. The IRCF bits may be modified at any time to

immediately change the clock speed.

On transitions from RC_RUN mode to PRI_RUN mode,

the device continues to be clocked from the internal

oscillator block while the primary oscillator is started.

When the primary oscillator becomes ready, a clock

switch to the primary clock occurs. When the clock

switch is complete, the IOFS bit is cleared, the OSTS

bit is set and the primary oscillator is providing the main

system clock. The HFINTOSC will continue to run if any

of the conditions noted in Section 2.5.2 “HFINTOSC”

are met. The LFINTOSC source will continue to run if

any of the conditions noted in Section 2.5.3 “LFIN-

TOSC” are met.

3.3

Sleep Mode

The Power-Managed Sleep mode in the PIC18F2XK20/

4XK20 devices is identical to the legacy Sleep mode

offered in all other PIC® microcontroller devices. It is

entered by clearing the IDLEN bit (the default state on

device Reset) and executing the SLEEP instruction.

This shuts down the selected oscillator (Figure 3-1). All

clock source Status bits are cleared.

Entering the Sleep mode from any other mode does not

require a clock switch. This is because no clocks are

needed once the controller has entered Sleep. If the

WDT is selected, the LFINTOSC source will continue to

operate. If the Timer1 oscillator is enabled, it will also

continue to run.

When a wake event occurs in Sleep mode (by interrupt,

Reset or WDT time-out), the device will not be clocked

until the clock source selected by the SCS<1:0> bits

becomes ready (see Figure 3-2), or it will be clocked

from the internal oscillator block if either the Two-Speed

Start-up or the Fail-Safe Clock Monitor are enabled

(see Section 23.0 “Special Features of the CPU”). In

either case, the OSTS bit is set when the primary clock

is providing the device clocks. The IDLEN and SCS bits

are not affected by the wake-up.

3.4

Idle Modes

The Idle modes allow the controller’s CPU to be

selectively shut down while the peripherals continue to

operate. Selecting a particular Idle mode allows users

to further manage power consumption.

If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is

executed, the peripherals will be clocked from the clock

source selected by the SCS<1:0> bits; however, the CPU

will not be clocked. The clock source Status bits are not

affected. Setting IDLEN and executing a SLEEP instruc-

tion provides a quick method of switching from a given

Run mode to its corresponding Idle mode.

If the WDT is selected, the LFINTOSC source will con-

tinue to operate. If the Timer1 oscillator is enabled, it

will also continue to run.

Since the CPU is not executing instructions, the only

exits from any of the Idle modes are by interrupt, WDT

time-out, or a Reset. When a wake event occurs, CPU

execution

delayed

interval

TCSD

(parameter 38, Table 26-10) while it becomes ready to

execute code. When the CPU begins executing code,

it resumes with the same clock source for the current

Idle mode. For example, when waking from RC_IDLE

mode, the internal oscillator block will clock the CPU

and peripherals (in other words, RC_RUN mode). The

IDLEN and SCS bits are not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT

time-out will result in a WDT wake-up to the Run mode

currently specified by the SCS<1:0> bits.

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