PIC18F23K20-ESLASHML datasheet(135/456 Pages) MICROCHIP

135 / 456 page

 2010 Microchip Technology Inc.

DS41303G-page 135

PIC18F2XK20/4XK20

TABLE 10-9:

PORTE I/O SUMMARY

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Function

TRIS

Setting

I/O

Type

Description

RE0/RD/AN5

RE0

DIG

LATE<0> data output; not affected by analog input.

PORTE<0> data input; disabled when analog input enabled.

TTL

PSP read enable input (PSP enabled).

AN5

ANA

A/D input channel 5; default input configuration on POR.

RE1/WR/AN6

RE1

DIG

LATE<1> data output; not affected by analog input.

PORTE<1> data input; disabled when analog input enabled.

TTL

PSP write enable input (PSP enabled).

AN6

ANA

A/D input channel 6; default input configuration on POR.

RE2/CS/AN7

RE2

DIG

LATE<2> data output; not affected by analog input.

PORTE<2> data input; disabled when analog input enabled.

TTL

PSP write enable input (PSP enabled).

AN7

ANA

A/D input channel 7; default input configuration on POR.

MCLR/VPP/

RE3(1,2)

MCLR

—

External Master Clear input; enabled when MCLRE Configuration bit is

set.

VPP

—

ANA

High-voltage detection; used for ICSP™ mode entry detection. Always

available, regardless of pin mode.

RE3

—(2)

PORTE<3> data input; enabled when MCLRE Configuration bit is

clear.

Legend:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

= Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note

RE3 is available on both PIC18F2XK20 and PIC18F4XK20 devices. All other PORTE pins are only implemented on

PIC18F4XK20 devices.

RE3 does not have a corresponding TRIS bit to control data direction.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

PORTE

—

—RE3(1,2)

RE2

RE1

RE0

LATE(2)

—

LATE Data Output Register

TRISE(3)

IBF

OBF

IBOV

PSPMODE

—

TRISE2

TRISE1

TRISE0

SLRCON

—

—SLRE(3)

SLRD(3)

SLRC

SLRB

SLRA

ANSEL

ANS7(3)

ANS6(3)

ANS5(3)

ANS4

ANS3

ANS2

ANS1

ANS0

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.

Note 1:

Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).

RE3 is the only PORTE bit implemented on both PIC18F2XK20 and PIC18F4XK20 devices. All other bits

are implemented only when PORTE is implemented (i.e., PIC18F4XK20 devices).

Unimplemented on PIC18F2XK20 devices.

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