PIC18F23K20-ESLASHML datasheet(133/456 Pages) MICROCHIP

133 / 456 page

 2010 Microchip Technology Inc.

DS41303G-page 133

PIC18F2XK20/4XK20

10.6

PORTE, TRISE and LATE

Registers

Depending on the particular PIC18F2XK20/4XK20

device selected, PORTE is implemented in two

different ways.

10.6.1

PORTE IN PIC18F4XK20 DEVICES

For PIC18F4XK20 devices, PORTE is a 4-bit wide port.

Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/

AN7) are individually configurable as inputs or outputs.

These pins have Schmitt Trigger input buffers. When

selected as an analog input, these pins will read as ‘0’s.

The corresponding data direction register is TRISE.

Setting a TRISE bit (= 1) will make the corresponding

PORTE pin an input (i.e., disable the output driver).

Clearing a TRISE bit (= 0) will make the corresponding

PORTE pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

TRISE controls the direction of the RE pins, even when

they are being used as analog inputs. The user must

make sure to keep the pins configured as inputs when

using them as analog inputs.

The upper four bits of the TRISE register also control

the operation of the Parallel Slave Port. Their operation

is explained in Register 10-1.

The Data Latch register (LATE) is also memory

mapped. Read-modify-write operations on the LATE

PORTE.

The fourth pin of PORTE (MCLR/VPP/RE3) is an input

only pin. Its operation is controlled by the MCLRE

Configuration bit. When selected as a port pin

(MCLRE = 0), it functions as a digital input only pin; as

such, it does not have TRIS or LAT bits associated with its

operation. Otherwise, it functions as the device’s Master

Clear input. In either configuration, RE3 also functions as

the programming voltage input during programming.

EXAMPLE 10-5:

INITIALIZING PORTE

10.6.2

PORTE IN PIC18F2XK20 DEVICES

For PIC18F2XK20 devices, PORTE is only available

when

Master

Clear

functionality

disabled

(MCLR = 0). In these cases, PORTE is a single bit,

input only port comprised of RE3 only. The pin operates

as previously described.

Note:

On a Power-on Reset, RE<2:0> are

configured as analog inputs.

Note:

On a Power-on Reset, RE3 is enabled as

a digital input only if Master Clear

functionality is disabled.

CLRF

PORTE

; Initialize PORTE by

; clearing output

; data latches

CLRF

LATE

; Alternate method

; to clear output

; data latches

MOVLW

1Fh

; Configure analog pins

ANDWF

ANSEL,w ; for digital only

MOVLW

05h

; Value used to

; initialize data

; direction

MOVWF

TRISE

; Set RE<0> as input

; RE<1> as output

; RE<2> as input

PIC18F23K20-E/ML датащи(PDF) 133 Page - Microchip Technology

PIC18F23K20-E/ML датащи(HTML) 133 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL