PCF8562TTSLASH2 datasheet(28/36 Pages) NXP

28 / 36 page

PCF8562_4

Product data sheet

Rev. 04 — 18 March 2009

28 of 36

NXP Semiconductors

PCF8562

Universal LCD driver for low multiplex rates

11. Dynamic characteristics

[1]

Typical output duty factor: 50 % measured at the CLK output pin.

[2]

Not tested in production.

[3]

All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an

input voltage swing of VSS to VDD.

Table 17.

Dynamic characteristics

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Clock

fclk(int)

internal clock frequency

[1]

1440

1850

2640

fclk(ext)

external clock frequency

960

2640

tclk(H)

HIGH-level clock time

µs

tclk(L)

LOW-level clock time

µs

Synchronization

tPD(SYNC_N) SYNC propagation delay

tSYNC_NL

SYNC LOW time

µs

tPD(drv)

driver propagation delay

VLCD = 5 V

[2]

--30

µs

I2C-bus[3]

Pin SCL

fSCL

SCL clock frequency

400

kHz

tLOW

LOW period of the SCL clock

1.3

µs

tHIGH

HIGH period of the SCL clock

0.6

µs

Pin SDA

tSU;DAT

data set-up time

100

tHD;DAT

data hold time

Pins SCL and SDA

tBUF

bus free time between a STOP and

START condition

1.3

µs

tSU;STO

set-up time for STOP condition

0.6

µs

tHD;STA

hold time (repeated) START condition

0.6

µs

tSU;STA

set-up time for a repeated START

condition

0.6

µs

rise time of both SDA and SCL signals

fSCL = 400 kHz

0.3

µs

fSCL < 125 kHz

1.0

µs

fall time of both SDA and SCL signals

0.3

µs

capacitive load for each bus line

400

tw(spike)

spike pulse width

on the I2C-bus

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