PCF8562TTSLASH2 datasheet(20/36 Pages) NXP

20 / 36 page

PCF8562_4

Product data sheet

Rev. 04 — 18 March 2009

20 of 36

NXP Semiconductors

PCF8562

Universal LCD driver for low multiplex rates

7.16.4 Acknowledge

The number of data bytes that can be transferred from transmitter to receiver between the

START and STOP conditions is unlimited. Each byte of eight bits is followed by an

acknowledge bit. The acknowledge bit is a HIGH-level signal on the bus that is asserted

by the transmitter during which time the master generates an extra acknowledge related

clock pulse. An addressed slave receiver must generate an acknowledge after receiving

each byte. Also a master receiver must generate an acknowledge after receiving each

byte that has been clocked out of the slave transmitter. The acknowledging device must

pull-down the SDA line during the acknowledge clock pulse so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold

times must be taken into consideration). A master receiver must signal an end of data to

the transmitter by not generating an acknowledge on the last byte that has been clocked

out of the slave. In this event the transmitter must leave the data line HIGH to enable the

master to generate a STOP condition (see Figure 14).

7.16.5 I2C-bus controller

The PCF8562 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or

transmit data to an I2C-bus master receiver. The only data output from the PCF8562 are

the acknowledge signals of the selected devices. Device selection depends on the

I2C-bus slave address, on the transferred command data and on the hardware

subaddress.

Fig 13. System conﬁguration

mga807

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

Fig 14. Acknowledgement of the I2C-bus

mbc602

START

condition

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

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