PCF8562TTSLASH2 datasheet(27/36 Pages) NXP

27 / 36 page

PCF8562_4

Product data sheet

Rev. 04 — 18 March 2009

27 of 36

NXP Semiconductors

PCF8562

Universal LCD driver for low multiplex rates

10. Static characteristics

[1]

VLCD > 3 V for 1⁄3 bias.

[2]

LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.

[3]

When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 15 (see Figure 17

too).

[4]

Propagation delay of driver between clock (CLK) and LCD driving signals.

[5]

Periodically sampled, not 100 % tested.

[6]

Outputs measured one at a time.

Table 16.

Static characteristics

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies

VDD

supply voltage

1.8

5.5

VLCD

LCD supply voltage

[1]

2.5

6.5

IDD

supply current

fclk = 1536 Hz

[2]

-8

µA

IDD(LCD)

LCD supply current

fclk = 1536 Hz

[2]

-24

µA

Logic

VP(POR)

power-on reset supply voltage

1.0

1.3

1.6

VIL

LOW-level input voltage

on pins CLK, SYNC,

OSC, A0 to A2, SA0,

SCL, SDA

VSS

0.3VDD

VIH

HIGH-level input voltage

on pins CLK, SYNC,

OSC, A0 to A2, SA0,

SCL, SDA

[3][4]

0.7VDD

-VDD

IOL

LOW-level output current

VOL = 0.4 V; VDD =5V

on pins CLK and SYNC

on pin SDA

IOH(CLK)

HIGH-level output current on pin CLK

VOH = 4.6 V; VDD =5V

−1-

leakage current

VI =VDD or VSS;

on pins CLK, SCL, SDA,

A0 to A2 and SA0

−1-

µA

IL(OSC)

leakage current on pin OSC

VI =VDD

−1-

µA

input capacitance

[5]

--7

LCD outputs

∆VO

output voltage variation

on pins BP0 to BP3 and

S0 to S31

−100

+100

output resistance

VLCD = 5 V

[6]

on pins BP0 to BP3

1.5

Ω

on pins S0 to S31

6.0

Ω

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