PCF8562TTSLASH2 datasheet(15/36 Pages) NXP

15 / 36 page

PCF8562_4

Product data sheet

Rev. 04 — 18 March 2009

15 of 36

NXP Semiconductors

PCF8562

Universal LCD driver for low multiplex rates

7.10 Display RAM

The display RAM is a static 32

× 4-bit RAM which stores LCD data. A logic 1 in the RAM

bit-map indicates the on-state of the corresponding LCD element; similarly, a logic 0

indicates the off-state. There is a one-to-one correspondence between the RAM

addresses and the segment outputs, and between the individual bits of a RAM word and

the backplane outputs. The display RAM bit map Figure 9 shows the rows 0 to 3 which

correspond with the backplane outputs BP0 to BP3, and the columns 0 to 31 which

correspond with the segment outputs S0 to S31. In multiplexed LCD applications the

segment data of the ﬁrst, second, third and fourth row of the display RAM are

time-multiplexed with BP0, BP1, BP2 and BP3 respectively.

When display data is transmitted to the PCF8562, the display bytes received are stored in

the display RAM in accordance with the selected LCD drive mode. The data is stored as it

arrives and does not wait for an acknowledge cycle as with the commands. Depending on

the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets.

To illustrate the ﬁlling order, an example of a 7-segment numeric display showing all drive

modes is given in Figure 10; the RAM ﬁlling organization depicted applies equally to other

LCD types.

The following applies to Figure 10:

• In the static drive mode, the eight transmitted data bits are placed in row 0 of eight

successive 4-bit RAM words.

• In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into

row 0 and 1 of four successive 4-bit RAM words.

• In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1 and 2 to

three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difﬁcult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted.

• In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into

row 0, 1, 2 and 3 of two successive 4-bit RAM words.

Display RAM bit map showing direct relationship between RAM addresses and segment outputs;

also between bits in a RAM word and the backplane outputs.

Fig 9.

Display RAM bit map

1234

display RAM addresses (rows) / segment outputs (S)

display RAM bits

(columns) /

backplane outputs

(BP)

001aac265

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